i965/barrier: Do the correct flushes for framebuffer access

Framebuffer access includes framebuffer reads so we need to invalidate
the texture cache.  We do not, however, need to flush the depth cache
because you cannot do bind a depth texture as an image.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 3743fa9b5eb849e1120eddd9d3b5af4ffd69f5b5..c11ac871e58e7c43b60a5f92f26ea06a319005c1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -274,7 +274,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
                PIPE_CONTROL_RENDER_TARGET_FLUSH);
 
    if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
-      bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+      bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
                PIPE_CONTROL_RENDER_TARGET_FLUSH);
 
    /* Typed surface messages are handled by the render cache on IVB, so we