# list of ISAs from env['ALL_ISA_LIST'].
def gen_switch_hdr(target, source, env):
fname = str(target[0])
- bname = basename(fname)
f = open(fname, 'w')
- f.write('#include "arch/isa_specific.hh"\n')
- cond = '#if'
- for isa in all_isa_list:
- f.write('%s THE_ISA == %s_ISA\n#include "%s/%s/%s"\n'
- % (cond, isa.upper(), dname, isa, bname))
- cond = '#elif'
- f.write('#else\n#error "THE_ISA not set"\n#endif\n')
+ isa = env['TARGET_ISA'].lower()
+ print >>f, '#include "%s/%s/%s"' % (dname, isa, basename(fname))
f.close()
- return 0
# String to print when generating header
def gen_switch_hdr_string(target, source, env):
for extra_dir in extras_dir_list:
env.Append(CPPPATH=Dir(extra_dir))
-# Add a flag defining what THE_ISA should be for all compilation
-env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
-
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308
for root, dirs, files in os.walk(base_dir, topdown=True):
for opt in export_vars:
env.ConfigFile(opt)
+def makeTheISA(source, target, env):
+ f = file(str(target[0]), 'w')
+
+ isas = [ src.get_contents() for src in source ]
+ target = env['TARGET_ISA']
+ def define(isa):
+ return isa.upper() + '_ISA'
+
+ def namespace(isa):
+ return isa[0].upper() + isa[1:].lower() + 'ISA'
+
+
+ print >>f, '#ifndef __CONFIG_THE_ISA_HH__'
+ print >>f, '#define __CONFIG_THE_ISA_HH__'
+ print >>f
+ for i,isa in enumerate(isas):
+ print >>f, '#define %s %d' % (define(isa), i + 1)
+ print >>f
+ print >>f, '#define THE_ISA %s' % (define(target))
+ print >>f, '#define TheISA %s' % (namespace(target))
+ print >>f
+ print >>f, '#endif // __CONFIG_THE_ISA_HH__'
+
+env.Command('config/the_isa.hh', map(Value, all_isa_list), makeTheISA)
+
########################################################################
#
# Prevent any SimObjects from being added after this point, they
#define __ARCH_ARM_STACKTRACE_HH__
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
class ThreadContext;
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ISA_SPECIFIC_HH__
-#define __ARCH_ISA_SPECIFIC_HH__
-
-//This file provides a mechanism for other source code to bring in
-//files from the ISA being compiled in.
-
-//These are constants so you can selectively compile code based on the isa.
-//To use them, do something like:
-//
-//#if THE_ISA == YOUR_FAVORITE_ISA
-// conditional_code
-//#endif
-//
-//Note that this is how this file sets up the TheISA macro.
-
-//These macros have numerical values because otherwise the preprocessor
-//would treat them as 0 in comparisons.
-#define ALPHA_ISA 21064
-#define SPARC_ISA 42
-#define MIPS_ISA 34000
-#define X86_ISA 8086
-#define ARM_ISA 6
-
-//These tell the preprocessor where to find the files of a particular
-//ISA, and set the "TheISA" macro for use elsewhere.
-#if THE_ISA == ALPHA_ISA
- #define TheISA AlphaISA
-#elif THE_ISA == SPARC_ISA
- #define TheISA SparcISA
-#elif THE_ISA == MIPS_ISA
- #define TheISA MipsISA
-#elif THE_ISA == X86_ISA
- #define TheISA X86ISA
-#elif THE_ISA == ARM_ISA
- #define TheISA ArmISA
-#else
- #error "THE_ISA not set"
-#endif
-
-#endif
#include "base/loader/object_file.hh"
#include "base/output.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "sim/arguments.hh"
#include "sim/core.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/cp_annotate.hh"
+#include "config/the_isa.hh"
#include "sim/serialize.hh"
#include "sim/startup.hh"
#include "sim/system.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
-//#include "mem/physical.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "sim/system.hh"
#include "arch/microcode_rom.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "sim/eventq.hh"
#include "sim/insttracer.hh"
#include "mem/mem_object.hh"
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
-
-#include "sim/faults.hh"
+#include "config/the_isa.hh"
+#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "mem/request.hh"
-
-#include "cpu/base_dyn_inst.hh"
+#include "sim/faults.hh"
#define NOHASH
#ifndef NOHASH
#include <string>
#include "base/refcnt.hh"
+#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
#include "arch/types.hh"
+#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "config/the_isa.hh"
#include "enums/OpClass.hh"
using namespace std;
#include "arch/utility.hh"
#include "config/full_system.hh"
-#include "cpu/exetrace.hh"
+#include "config/the_isa.hh"
#include "cpu/activity.hh"
-#include "cpu/simple_thread.hh"
-#include "cpu/thread_context.hh"
#include "cpu/base.hh"
-#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/thread_context.hh"
-#include "cpu/inorder/thread_state.hh"
+#include "cpu/exetrace.hh"
#include "cpu/inorder/cpu.hh"
-#include "params/InOrderCPU.hh"
-#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/first_stage.hh"
-#include "cpu/inorder/resources/resource_list.hh"
+#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
+#include "cpu/inorder/resources/resource_list.hh"
+#include "cpu/inorder/thread_context.hh"
+#include "cpu/inorder/thread_state.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
#include "mem/translating_port.hh"
+#include "params/InOrderCPU.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
#include "base/timebuf.hh"
#include "base/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include <string>
#include <sstream>
+#include "arch/faults.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
-
-#include "arch/faults.hh"
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
-#include "mem/request.hh"
-
-#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/cpu.hh"
+#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "mem/request.hh"
using namespace std;
using namespace TheISA;
#include <list>
#include <string>
-#include "arch/isa_traits.hh"
#include "arch/faults.hh"
-#include "arch/types.hh"
+#include "arch/isa_traits.hh"
#include "arch/mt.hh"
+#include "arch/types.hh"
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "base/types.hh"
-#include "cpu/inorder/inorder_trace.hh"
#include "config/full_system.hh"
-#include "cpu/thread_context.hh"
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
+#include "cpu/inorder/inorder_trace.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/resource.hh"
+#include "cpu/inorder/thread_state.hh"
#include "cpu/inst_seq.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
-#include "cpu/inorder/thread_state.hh"
-#include "cpu/inorder/resource.hh"
-#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/thread_context.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
-#include "sim/faults.hh"
-#if THE_ISA==ALPHA_ISA
+#if THE_ISA == ALPHA_ISA
#include "arch/alpha/ev5.hh"
#endif
#include <iomanip>
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/inorder/inorder_trace.hh"
#include "cpu/static_inst.hh"
*/
#include "base/str.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_stage.hh"
#include "cpu/inorder/resource_pool.hh"
#include "cpu/inorder/cpu.hh"
*/
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/reg_dep_map.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include <vector>
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_traits.hh"
class InOrderCPU;
#include "base/trace.hh"
#include "base/traceflags.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/resources/bpred_unit.hh"
using namespace std;
*
*/
+#include "config/the_isa.hh"
#include "cpu/inorder/resources/branch_predictor.hh"
using namespace std;
#include <vector>
#include <list>
+
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/utility.hh"
#include "arch/predecoder.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/resources/cache_unit.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/cpu.hh"
#include <list>
#include <string>
-#include "arch/tlb.hh"
#include "arch/predecoder.hh"
-#include "cpu/inorder/resource.hh"
+#include "arch/tlb.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
+#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/resource.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
-#include "cpu/inorder/pipeline_traits.hh"
-#include "sim/sim_object.hh"
-
#include "params/InOrderCPU.hh"
+#include "sim/sim_object.hh"
class CacheRequest;
typedef CacheRequest* CacheReqPtr;
*
*/
+#include "config/the_isa.hh"
#include "cpu/inorder/resources/decode_unit.hh"
using namespace TheISA;
*
*/
+#include "config/the_isa.hh"
#include "cpu/inorder/resources/fetch_seq_unit.hh"
#include "cpu/inorder/resource_pool.hh"
#include <list>
#include <string>
+#include "config/the_isa.hh"
#include "cpu/inorder/resource.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include <vector>
#include <list>
+
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resources/inst_buffer.hh"
#include "cpu/inorder/cpu.hh"
#include <vector>
#include <list>
+
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resources/inst_buffer.hh"
#include "cpu/inorder/cpu.hh"
#include <vector>
#include <list>
+
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/first_stage.hh"
#include "cpu/inorder/resources/tlb_unit.hh"
#include <list>
#include <string>
+#include "config/the_isa.hh"
#include "cpu/inorder/resources/inst_buffer.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include <vector>
#include <list>
+
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resources/use_def.hh"
#include "cpu/inorder/cpu.hh"
*/
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/inorder/thread_context.hh"
#ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
#define __CPU_INORDER_THREAD_CONTEXT_HH__
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/thread_context.hh"
#include "cpu/inorder/thread_state.hh"
#include <iomanip>
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/inteltrace.hh"
#include "cpu/static_inst.hh"
* Steve Raasch
*/
-#include "arch/isa_specific.hh"
+#include "config/the_isa.hh"
#if THE_ISA != SPARC_ISA
#error Legion tracing only works with SPARC simulations!
#endif
* Authors: Kevin Lim
*/
+#include <algorithm>
+
#include "arch/types.hh"
#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/bpred_unit.hh"
-
#include "params/DerivO3CPU.hh"
-#include <algorithm>
-
template<class Impl>
BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params)
: _name(params->name + ".BPredUnit"),
#include "base/loader/symtab.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/commit.hh"
*/
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
-
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
* Authors: Kevin Lim
*/
+#include "config/the_isa.hh"
#include "cpu/o3/decode.hh"
#include "params/DerivO3CPU.hh"
#define __CPU_O3_DYN_INST_HH__
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/cpu.hh"
#include "arch/predecoder.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
+#include "config/the_isa.hh"
#include "cpu/pc_event.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
/**
#include <queue>
#include "base/timebuf.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
#include "params/DerivO3CPU.hh"
#define __CPU_O3_IMPL_HH__
#include "arch/isa_traits.hh"
-
+#include "config/the_isa.hh"
#include "cpu/o3/cpu_policy.hh"
#include "arch/faults.hh"
#include "arch/locked_mem.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
*/
#include "arch/locked_mem.hh"
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
-
#include "cpu/o3/lsq.hh"
#include "cpu/o3/lsq_unit.hh"
#include "base/str.hh"
#ifndef __CPU_O3_REGFILE_HH__
#define __CPU_O3_REGFILE_HH__
+#include <vector>
+
#include "arch/isa_traits.hh"
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#endif
-#include <vector>
-
/**
* Simple physical register file class.
* Right now this is specific to Alpha until we decide if/how to make things
#include "base/statistics.hh"
#include "base/timebuf.hh"
+#include "config/the_isa.hh"
class DerivO3CPUParams;
#include "arch/isa_traits.hh"
#include "arch/registers.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/rename.hh"
#include "params/DerivO3CPU.hh"
#include <utility>
#include <vector>
-#include "cpu/o3/free_list.hh"
#include "arch/types.hh"
+#include "config/the_isa.hh"
+#include "cpu/o3/free_list.hh"
class SimpleRenameMap
{
#include <utility>
#include <vector>
+#include "config/the_isa.hh"
+
/**
* ROB class. The ROB is largely what drives squashing.
*/
* Kevin Lim
*/
-#include "arch/isa_specific.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/scoreboard.hh"
Scoreboard::Scoreboard(unsigned activeThreads,
#ifndef __CPU_O3_THREAD_CONTEXT_HH__
#define __CPU_O3_THREAD_CONTEXT_HH__
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/isa_specific.hh"
*/
#include "arch/registers.hh"
+#include "config/the_isa.hh"
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/inst_seq.hh"
#include "arch/isa_traits.hh" // For MachInst
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "arch/isa_traits.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/cpu.hh" // MUST include this
#include "sim/faults.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/ozone/dyn_inst.hh"
#if FULL_SYSTEM
#include "arch/utility.hh"
#include "base/timebuf.hh"
+#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/bpred_unit.hh"
#include "cpu/ozone/rename_table.hh"
* Authors: Kevin Lim
*/
-#include "config/use_checker.hh"
-
#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/statistics.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
#include "sim/faults.hh"
#include "arch/types.hh"
+#include "config/the_isa.hh"
#include "cpu/ozone/inorder_back_end.hh"
#include "cpu/ozone/thread_state.hh"
#include "arch/faults.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "mem/mem_interface.hh"
#include "arch/faults.hh"
#include "base/str.hh"
+#include "config/the_isa.hh"
#include "cpu/ozone/lsq_unit.hh"
template <class Impl>
* Authors: Kevin Lim
*/
+#include "config/the_isa.hh"
#include "config/use_checker.hh"
-
#include "cpu/ozone/lw_back_end.hh"
#include "cpu/op_class.hh"
#include "arch/faults.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
* Authors: Kevin Lim
*/
-#include "config/use_checker.hh"
-
#include "arch/faults.hh"
#include "base/str.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
#include "cpu/ozone/lw_lsq.hh"
#include "cpu/checker/cpu.hh"
#define __CPU_OZONE_RENAME_TABLE_HH__
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
/** Rename table that holds the rename of each architectural register to
* producing DynInst. Needs to support copying from one table to another.
*/
#include <cstdlib> // Not really sure what to include to get NULL
+
+#include "config/the_isa.hh"
#include "cpu/ozone/rename_table.hh"
template <class Impl>
#ifndef __CPU_OZONE_SIMPLE_PARAMS_HH__
#define __CPU_OZONE_SIMPLE_PARAMS_HH__
+#include "config/the_isa.hh"
#include "cpu/ozone/cpu.hh"
//Forward declarations
#ifndef __CPU_OZONE_THREAD_STATE_HH__
#define __CPU_OZONE_THREAD_STATE_HH__
-#include "sim/faults.hh"
-#include "arch/types.hh"
#include "arch/regfile.hh"
+#include "arch/types.hh"
#include "base/callback.hh"
#include "base/output.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+#include "sim/faults.hh"
#include "sim/process.hh"
#include "sim/sim_exit.hh"
#include <map>
#include "arch/stacktrace.hh"
+#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
#include "base/types.hh"
#include "arch/mmaped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/simple/atomic.hh"
#include "mem/packet.hh"
#include "base/stats/events.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/profile.hh"
#include "arch/predecoder.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/pc_event.hh"
#include "arch/mmaped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
+#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/simple/timing.hh"
#include "mem/packet.hh"
#include <string>
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "arch/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "mem/request.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
+#include "config/the_isa.hh"
#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/misc.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
void
#include "arch/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/faults.hh"
#define __CPU_THREAD_STATE_HH__
#include "arch/types.hh"
+#include "config/the_isa.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include <string>
#include <vector>
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "dev/alpha/tsunami_cchip.hh"
#include "dev/alpha/tsunami_pchip.hh"
#include "arch/alpha/ev5.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "dev/alpha/tsunami.hh"
#include "base/time.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/rtcreg.h"
#include "dev/alpha/tsunami_cchip.hh"
#include "dev/alpha/tsunami.hh"
#include <vector>
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/alpha/tsunami_pchip.hh"
#include "dev/alpha/tsunamireg.h"
#include "dev/alpha/tsunami.hh"
#include <vector>
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/baddev.hh"
#include "dev/platform.hh"
#include "mem/port.hh"
#include <string>
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "base/chunk_generator.hh"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include <string>
#include <vector>
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_pchip.hh"
#include "params/Malta.hh"
#include "sim/system.hh"
-
using namespace std;
using namespace TheISA;
#include "arch/mips/mips_core_specific.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "dev/mips/malta.hh"
MaltaCChip::MaltaCChip(Params *p)
: BasicPioDevice(p), malta(p->malta)
{
- warn("MaltaCCHIP::MaltaCChip() not implemented.");
+ warn("MaltaCCHIP::MaltaCChip() not implemented.");
pioSize = 0xfffffff;
//Put back pointer in malta
#include "base/time.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/rtcreg.h"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta.hh"
#include <vector>
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/mips/malta_pchip.hh"
#include "dev/mips/maltareg.h"
#include "dev/mips/malta.hh"
#include "base/debug.hh"
#include "base/inet.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
*/
#include "base/misc.hh"
+#include "config/the_isa.hh"
#include "dev/platform.hh"
#include "sim/sim_exit.hh"
#include "base/debug.hh"
#include "base/inet.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "base/time.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/sparc/dtod.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include <string>
#include <vector>
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "dev/sparc/t1000.hh"
#include "dev/terminal.hh"
#include "base/inifile.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "dev/platform.hh"
#include "dev/terminal.hh"
#include "dev/uart8250.hh"
#include "arch/x86/intmessage.hh"
#include "arch/x86/x86_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "dev/terminal.hh"
#include "dev/x86/i82094aa.hh"
#ifndef __PRINTK_HH__
#define __PRINTK_HH__
-#include "arch/isa_specific.hh"
-
#include <sstream>
class Arguments;
* Nathan Binkert
*/
-//For ISA_HAS_DELAY_SLOT
#include "arch/isa_traits.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "kern/system_events.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/mbuf.hh"
#include "sim/arguments.hh"
#ifndef __TRU64_HH__
#define __TRU64_HH__
+
#include "config/full_system.hh"
#include "kern/operatingsystem.hh"
#include <string.h> // for memset()
#include <unistd.h>
+#include "config/the_isa.hh"
#include "arch/alpha/registers.hh"
#include "cpu/base.hh"
#include "sim/core.hh"
#include "arch/alpha/ev5.hh"
#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "kern/system_events.hh"
* @file
* Simobject instatiation of caches.
*/
+#include <list>
#include <vector>
-// Must be included first to determine which caches we want
+#include "config/the_isa.hh"
#include "enums/Prefetch.hh"
#include "mem/config/cache.hh"
#include "mem/cache/base.hh"
* Hardware Prefetcher Definition.
*/
+#include <list>
+
#include "arch/isa_traits.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "mem/cache/base.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/request.hh"
-#include <list>
BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
: size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
#include "arch/isa_traits.hh"
#include "base/bigint.hh"
+#include "config/the_isa.hh"
#include "mem/packet.hh"
#include "sim/byteswap.hh"
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
#include "arch/tlb.hh"
#include "base/hashmap.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
#include "sim/serialize.hh"
#include "base/random.hh"
#include "base/types.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
#include "sim/eventq.hh"
* Authors: Ali Saidi
*/
-//To get endianness
#include "arch/isa_traits.hh"
-
+#include "config/the_isa.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
#include "base/output.hh"
#include "base/str.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "mem/ruby/common/Debug.hh"
#include "mem/ruby/libruby.hh"
#include "mem/ruby/system/RubyPort.hh"
*/
#include <string>
+
#include "base/chunk_generator.hh"
+#include "config/the_isa.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "mem/page_table.hh"
*/
#include "base/chunk_generator.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "mem/vport.hh"
* Authors: Nathan Binkert
*/
-#include "sim/arguments.hh"
#include "arch/utility.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
-
-using namespace TheISA;
+#include "sim/arguments.hh"
Arguments::Data::~Data()
{
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "sim/syscall_emul.hh"
#include "sim/system.hh"
-#include "arch/isa_specific.hh"
#if THE_ISA == ALPHA_ISA
#include "arch/alpha/linux/process.hh"
#include "arch/alpha/tru64/process.hh"
#include "arch/registers.hh"
#include "base/statistics.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "sim/sim_object.hh"
#include "sim/syscallreturn.hh"
+class BaseRemoteGDB;
class GDBListener;
class PageTable;
class ProcessParams;
class System;
class ThreadContext;
class TranslatingPort;
-namespace TheISA
-{
- class RemoteGDB;
-}
template<class IntType>
struct AuxVector
std::vector<int> contextIds;
// remote gdb objects
- std::vector<TheISA::RemoteGDB *> remoteGDB;
+ std::vector<BaseRemoteGDB *> remoteGDB;
std::vector<GDBListener *> gdbListen;
bool breakpoint();
#include <fstream>
#include <string>
-#include "config/full_system.hh"
-
#include "arch/vtophys.hh"
#include "base/debug.hh"
+#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/quiesce_event.hh"
#include "sim/syscall_emul.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/system.hh"
-
#include "sim/sim_exit.hh"
using namespace std;
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/translating_port.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "config/full_system.hh"
+#include "config/the_isa.hh"
#include "mem/mem_object.hh"
#include "mem/physical.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
#include "sim/debug.hh"
+
#if FULL_SYSTEM
#include "arch/vtophys.hh"
#include "kern/kernel_stats.hh"
#include "mem/port.hh"
#include "params/System.hh"
#include "sim/sim_object.hh"
+
#if FULL_SYSTEM
#include "kern/system_events.hh"
#include "mem/vport.hh"
class Platform;
#endif
class GDBListener;
-namespace TheISA
-{
- class RemoteGDB;
-}
+class BaseRemoteGDB;
class System : public SimObject
{
#endif
public:
- std::vector<TheISA::RemoteGDB *> remoteGDB;
+ std::vector<BaseRemoteGDB *> remoteGDB;
std::vector<GDBListener *> gdbListen;
bool breakpoint();