nvc0: Add support for setting viewport index/layer from VS/TES
authorIlia Mirkin <imirkin@alum.mit.edu>
Wed, 19 Apr 2017 22:38:02 +0000 (18:38 -0400)
committerIlia Mirkin <imirkin@alum.mit.edu>
Fri, 21 Apr 2017 03:24:06 +0000 (23:24 -0400)
This enables support on GM200+ for:
 - GL_AMD_vertex_shader_layer
 - GL_AMD_vertex_shader_layer_viewport_index
 - GL_ARB_shader_viewport_layer_array

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
[lyude: add relnotes/TES cap]
Signed-off-by: Lyude <lyude@redhat.com>
[imirkin: move relnotes to right place, add features.txt]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
docs/features.txt
docs/relnotes/17.2.0.html
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c

index 5f63632e82cdad8b5307e3742029f634b5c9c6de..b62b5be42c291bcce347c42c10c6adb9e093d150 100644 (file)
@@ -297,7 +297,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_ARB_shader_draw_parameters                         DONE (i965, nvc0, radeonsi)
   GL_ARB_shader_group_vote                              DONE (nvc0, radeonsi)
   GL_ARB_shader_stencil_export                          DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr)
-  GL_ARB_shader_viewport_layer_array                    DONE (i965/gen6+, radeonsi)
+  GL_ARB_shader_viewport_layer_array                    DONE (i965/gen6+, nvc0, radeonsi)
   GL_ARB_sparse_buffer                                  DONE (radeonsi/CIK+)
   GL_ARB_sparse_texture                                 not started
   GL_ARB_sparse_texture2                                not started
index 5d9d7db44c9af18f98981e802d3e9f22bf346549..c96b18a91feee96071d1a5363c09ae42f6262f0c 100644 (file)
@@ -44,7 +44,9 @@ Note: some of the new features are only available with certain drivers.
 </p>
 
 <ul>
-TBD
+<li>GL_ARB_shader_viewport_layer_array on nvc0 (GM200+)</li>
+<li>GL_AMD_vertex_shader_layer on nvc0 (GM200+)</li>
+<li>GL_AMD_vertex_shader_viewport_index on nvc0 (GM200+)</li>
 </ul>
 
 <h2>Bug fixes</h2>
index 79a5333367e1c98045ed1c0c2691eeda8a6837a7..bd6f75238e5cd8db1a916eb9c2cfebbb55bd53e6 100644 (file)
@@ -312,6 +312,7 @@ void nvc0_fragprog_validate(struct nvc0_context *);
 void nvc0_compprog_validate(struct nvc0_context *);
 
 void nvc0_tfb_validate(struct nvc0_context *);
+void nvc0_layer_validate(struct nvc0_context *);
 
 /* nvc0_state.c */
 extern void nvc0_init_state_functions(struct nvc0_context *);
index e82f86909d59445b20eafd1fd2a3a6593d828bf5..13acef50216cfc2548a9174f53e6a0f2dd655da2 100644 (file)
@@ -258,6 +258,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_FS_FBFETCH:
       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+   case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+   case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
       return class_3d >= GM200_3D_CLASS;
    case PIPE_CAP_TGSI_BALLOT:
       return class_3d >= NVE4_3D_CLASS;
@@ -270,7 +272,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
-   case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
    case PIPE_CAP_FAKE_SW_MSAA:
    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
    case PIPE_CAP_VERTEXID_NOBASE:
@@ -291,7 +292,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_INT64_DIVMOD:
    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
-   case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index c644fe9925ec6ea8c9bb41cbb9ae9982894a84fb..a8c814fb372b15329528d81ce338369005ecb977 100644 (file)
@@ -220,18 +220,13 @@ nvc0_gmtyprog_validate(struct nvc0_context *nvc0)
 
    /* we allow GPs with no code for specifying stream output state only */
    if (gp && nvc0_program_validate(nvc0, gp) && gp->code_size) {
-      const bool gp_selects_layer = !!(gp->hdr[13] & (1 << 9));
-
       BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
       PUSH_DATA (push, 0x41);
       BEGIN_NVC0(push, NVC0_3D(SP_START_ID(4)), 1);
       PUSH_DATA (push, gp->code_base);
       BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(4)), 1);
       PUSH_DATA (push, gp->num_gprs);
-      BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
-      PUSH_DATA (push, gp_selects_layer ? NVC0_3D_LAYER_USE_GP : 0);
    } else {
-      IMMED_NVC0(push, NVC0_3D(LAYER), 0);
       BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
       PUSH_DATA (push, 0x40);
    }
@@ -251,6 +246,27 @@ nvc0_compprog_validate(struct nvc0_context *nvc0)
    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CODE);
 }
 
+void
+nvc0_layer_validate(struct nvc0_context *nvc0)
+{
+   struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+   struct nvc0_program *last;
+   bool prog_selects_layer = false;
+
+   if (nvc0->gmtyprog)
+      last = nvc0->gmtyprog;
+   else if (nvc0->tevlprog)
+      last = nvc0->tevlprog;
+   else
+      last = nvc0->vertprog;
+
+   if (last)
+      prog_selects_layer = !!(last->hdr[13] & (1 << 9));
+
+   BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
+   PUSH_DATA (push, prog_selects_layer ? NVC0_3D_LAYER_USE_GP : 0);
+}
+
 void
 nvc0_tfb_validate(struct nvc0_context *nvc0)
 {
index 68fd73064c8ecb513dc1276f182fabb6cf20d4e4..6d3caa116aea3bf5b9ae645937673bca376210a5 100644 (file)
@@ -878,6 +878,9 @@ validate_list_3d[] = {
     { nvc0_validate_buffers,       NVC0_NEW_3D_BUFFERS },
     { nvc0_idxbuf_validate,        NVC0_NEW_3D_IDXBUF },
     { nvc0_tfb_validate,           NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_GMTYPROG },
+    { nvc0_layer_validate,         NVC0_NEW_3D_VERTPROG |
+                                   NVC0_NEW_3D_TEVLPROG |
+                                   NVC0_NEW_3D_GMTYPROG },
     { nvc0_validate_driverconst,   NVC0_NEW_3D_DRIVERCONST },
 };