GL_ARB_shader_draw_parameters DONE (i965, nvc0, radeonsi)
GL_ARB_shader_group_vote DONE (nvc0, radeonsi)
GL_ARB_shader_stencil_export DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr)
- GL_ARB_shader_viewport_layer_array DONE (i965/gen6+, radeonsi)
+ GL_ARB_shader_viewport_layer_array DONE (i965/gen6+, nvc0, radeonsi)
GL_ARB_sparse_buffer DONE (radeonsi/CIK+)
GL_ARB_sparse_texture not started
GL_ARB_sparse_texture2 not started
</p>
<ul>
-TBD
+<li>GL_ARB_shader_viewport_layer_array on nvc0 (GM200+)</li>
+<li>GL_AMD_vertex_shader_layer on nvc0 (GM200+)</li>
+<li>GL_AMD_vertex_shader_viewport_index on nvc0 (GM200+)</li>
</ul>
<h2>Bug fixes</h2>
void nvc0_compprog_validate(struct nvc0_context *);
void nvc0_tfb_validate(struct nvc0_context *);
+void nvc0_layer_validate(struct nvc0_context *);
/* nvc0_state.c */
extern void nvc0_init_state_functions(struct nvc0_context *);
case PIPE_CAP_TGSI_FS_FBFETCH:
return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+ case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+ case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
return class_3d >= GM200_3D_CLASS;
case PIPE_CAP_TGSI_BALLOT:
return class_3d >= NVE4_3D_CLASS;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
- case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
return 0;
case PIPE_CAP_VENDOR_ID:
/* we allow GPs with no code for specifying stream output state only */
if (gp && nvc0_program_validate(nvc0, gp) && gp->code_size) {
- const bool gp_selects_layer = !!(gp->hdr[13] & (1 << 9));
-
BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
PUSH_DATA (push, 0x41);
BEGIN_NVC0(push, NVC0_3D(SP_START_ID(4)), 1);
PUSH_DATA (push, gp->code_base);
BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(4)), 1);
PUSH_DATA (push, gp->num_gprs);
- BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
- PUSH_DATA (push, gp_selects_layer ? NVC0_3D_LAYER_USE_GP : 0);
} else {
- IMMED_NVC0(push, NVC0_3D(LAYER), 0);
BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
PUSH_DATA (push, 0x40);
}
PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CODE);
}
+void
+nvc0_layer_validate(struct nvc0_context *nvc0)
+{
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+ struct nvc0_program *last;
+ bool prog_selects_layer = false;
+
+ if (nvc0->gmtyprog)
+ last = nvc0->gmtyprog;
+ else if (nvc0->tevlprog)
+ last = nvc0->tevlprog;
+ else
+ last = nvc0->vertprog;
+
+ if (last)
+ prog_selects_layer = !!(last->hdr[13] & (1 << 9));
+
+ BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
+ PUSH_DATA (push, prog_selects_layer ? NVC0_3D_LAYER_USE_GP : 0);
+}
+
void
nvc0_tfb_validate(struct nvc0_context *nvc0)
{
{ nvc0_validate_buffers, NVC0_NEW_3D_BUFFERS },
{ nvc0_idxbuf_validate, NVC0_NEW_3D_IDXBUF },
{ nvc0_tfb_validate, NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_GMTYPROG },
+ { nvc0_layer_validate, NVC0_NEW_3D_VERTPROG |
+ NVC0_NEW_3D_TEVLPROG |
+ NVC0_NEW_3D_GMTYPROG },
{ nvc0_validate_driverconst, NVC0_NEW_3D_DRIVERCONST },
};