r600: fix constant buffer size programming

When buffer size is less than 16, zero ends up being programmed as
size, which prevents the hardware from fetching the correct values.
Fix it by combining shift and align so that the value is always
rounded up.

Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 1443bc0c4afb40cd216b4c814957c19244a81fc4..1aee7dd2da8601ce19c4e19925705bd0d79d4632 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1956,7 +1956,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
 
                if (!gs_ring_buffer) {
                        radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
-                                                   ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
+                                                   ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags);
                        radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
                                                    pkt_flags);
                }

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e7ffe0dab1c216d702975bb15e4404107156bf0f..43b80742cb5c7b23f9c59690a14697341fa64fcb 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
 
                if (!gs_ring_buffer) {
                        radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
-                                              ALIGN_DIVUP(cb->buffer_size >> 4, 16));
+                                              ALIGN_DIVUP(cb->buffer_size, 256));
                        radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
                }