X86: Make sure there's something to catch when the kernel messes with ports "behind...

diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
index 86ae4c3ba553c674d70c7250666d2782d58c03fd..4ba9e7a8a57a1e3da1df783cd9014e9cd26e0cc4 100644 (file)
--- a/src/dev/x86/PC.py
+++ b/src/dev/x86/PC.py
@@ -50,6 +50,10 @@ class PC(Platform):
     # "Non-existant" port used for timing purposes by the linux kernel
     i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
 
+    # Ports behind the pci config and data regsiters. These don't do anything,
+    # but the linux kernel fiddles with them anway.
+    behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
+
     # Serial port and console
     console = SimConsole()
     com_1 = Uart8250()
@@ -59,6 +63,7 @@ class PC(Platform):
     def attachIO(self, bus):
         self.south_bridge.pio = bus.port
         self.i_dont_exist.pio = bus.port
+        self.behind_pci.pio = bus.port
         self.com_1.pio = bus.port
         self.pciconfig.pio = bus.default
         bus.responder_set = True