X86: Make conditional moves zero extend their 32 bit destinations always.

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 6921684a43f1a2cfb31a63897bc0072a85c0b744..dc6819886ef98ae18b803f5d1850d40b0eaee168 100644 (file)
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -639,7 +639,7 @@ let {{
 
     class Mov(CondRegOp):
         code = 'DestReg = merge(SrcReg1, op2, dataSize)'
-        else_code = 'DestReg=DestReg;'
+        else_code = 'DestReg = merge(DestReg, DestReg, dataSize);'
 
     # Shift instructions