Create a default selection stack in RTLIL::Design::Design()

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f237f57ef01d0f1f135aca0e14c5afb756945aed..35cd54b46f1b8ff909fcad759bde205921918e52 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -228,6 +228,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 RTLIL::Design::Design()
 {
        refcount_modules_ = 0;
+       selection_stack.push_back(RTLIL::Selection());
 }
 
 RTLIL::Design::~Design()

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 7b8173b6abf214b1caba04d8310b0e104acac8bf..0ecb4cdaf47e3d884a54764f60b44425cc7b4bb3 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire)
 void yosys_setup()
 {
        Pass::init_register();
-
        yosys_design = new RTLIL::Design;
-       yosys_design->selection_stack.push_back(RTLIL::Selection());
        log_push();
 }