For now, short $_DFF_[NP]_ from ff_map.v at re-integration

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f7f2e862a8c59075257804869066a37def2a75d4..69b0c1192e1bb967d52b1285530ea31d0449da9f 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -511,6 +511,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
                // Remove all AND, NOT, and ABC box instances
                // in preparation for stitching mapped_mod in
+               // Short $_DFF_[NP]_ cells used by ABC (FIXME)
                dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
                for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
                        RTLIL::Cell* cell = it->second;
@@ -518,6 +519,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                it = module->cells_.erase(it);
                                continue;
                        }
+                       else if (cell->type.in("$_DFF_N_", "$_DFF_P_")) {
+                               SigBit D = cell->getPort("\\D");
+                               SigBit Q = cell->getPort("\\Q");
+                               module->connect(Q, D);
+                               it = module->cells_.erase(it);
+                               continue;
+                       }
                        RTLIL::Module* box_module = design->module(cell->type);
                        if (box_module && box_module->attributes.count("\\abc_box_id")) {
                                erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));