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Merge pull request #1098 from YosysHQ/xaig
authorEddie Hung <eddie@fpgeh.com>
Fri, 28 Jun 2019 17:59:03 +0000 (10:59 -0700)
committerGitHub <noreply@github.com>
Fri, 28 Jun 2019 17:59:03 +0000 (10:59 -0700)
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)

1  2 
Makefile patch | diff1 | diff2 | blob | history

diff --cc Makefile
index 5ec3e03128e26dd6b821c9241997563dc8bccc22,6c5a436c1c75ef228f208d186fc8680ee5c108e6..d33f27b639024d614adf9e9327427df1c2c410e4
--- 1/Makefile
--- 2/Makefile
+++ b/Makefile
@@@ -686,8 -680,9 +686,9 @@@ test: $(TARGETS) $(EXTRA_TARGETS
        +cd tests/sat && bash run-test.sh
        +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
        +cd tests/opt && bash run-test.sh
 -      +cd tests/aiger && bash run-test.sh
 +      +cd tests/aiger && bash run-test.sh $(ABCOPT)
        +cd tests/arch && bash run-test.sh
+       +cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
        @echo ""
        @echo "  Passed \"make test\"."
        @echo ""