CPU: Don't fetch when executing a macroop.

If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 2ada12b8d8aec0807a66f8f7671e9c3a1dbbdc64..acda552d9e9042aab76b485436a3e4b5ef5f2703 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -607,7 +607,7 @@ AtomicSimpleCPU::tick()
         Fault fault = NoFault;
 
         bool fromRom = isRomMicroPC(thread->readMicroPC());
-        if (!fromRom) {
+        if (!fromRom && !curMacroStaticInst) {
             setupFetchRequest(&ifetch_req);
             fault = thread->itb->translateAtomic(&ifetch_req, tc);
         }
@@ -617,7 +617,7 @@ AtomicSimpleCPU::tick()
             bool icache_access = false;
             dcache_access = false; // assume no dcache access
 
-            if (!fromRom) {
+            if (!fromRom && !curMacroStaticInst) {
                 // This is commented out because the predecoder would act like
                 // a tiny cache otherwise. It wouldn't be flushed when needed
                 // like the I cache. It should be flushed, and when that works

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 3f5778138c220c00df44fb5d8105436a3ab6e366..f398365d375ab98ded05efa0abe7763c76335abe 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -667,7 +667,7 @@ TimingSimpleCPU::fetch()
 
     bool fromRom = isRomMicroPC(thread->readMicroPC());
 
-    if (!fromRom) {
+    if (!fromRom && !curMacroStaticInst) {
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);