--- /dev/null
+#!/usr/bin/env python3
+
+import sys
+import os
+import argparse
+import subprocess
+import struct
+import importlib
+
+from mibuild.tools import write_to_file
+from migen.util.misc import autotype
+from migen.fhdl import verilog, edif
+from migen.fhdl.structure import _Fragment
+from migen.bank.description import CSRStatus
+from mibuild import tools
+from mibuild.xilinx.common import *
+
+from misoclib.soc import cpuif
+#from misoclib.lit.liteusb.common import *
+
+
+def _import(default, name):
+ return importlib.import_module(default + "." + name)
+
+
+def _get_args():
+ parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
+ description="""\
+LiteUSB - based on Migen.
+
+This program builds and/or loads LiteUSB components.
+One or several actions can be specified:
+
+clean delete previous build(s).
+build-rtl build verilog rtl.
+build-bitstream build-bitstream build FPGA bitstream.
+build-csr-csv save CSR map into CSV file.
+
+load-bitstream load bitstream into volatile storage.
+
+all clean, build-csr-csv, build-bitstream, load-bitstream.
+""")
+
+ parser.add_argument("-t", "--target", default="simple", help="Core type to build")
+ parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
+ parser.add_argument("-p", "--platform", default=None, help="platform to build for")
+ parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
+ parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
+ parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
+
+ parser.add_argument("action", nargs="+", help="specify an action")
+
+ return parser.parse_args()
+
+# Note: misoclib need to be installed as a python library
+
+if __name__ == "__main__":
+ args = _get_args()
+
+ # create top-level Core object
+ target_module = _import("targets", args.target)
+ if args.sub_target:
+ top_class = getattr(target_module, args.sub_target)
+ else:
+ top_class = target_module.default_subtarget
+
+ if args.platform is None:
+ if hasattr(top_class, "default_platform"):
+ platform_name = top_class.default_platform
+ else:
+ raise ValueError("Target has no default platform, specify a platform with -p your_platform")
+ else:
+ platform_name = args.platform
+ platform_module = _import("mibuild.platforms", platform_name)
+ platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
+ platform = platform_module.Platform(**platform_kwargs)
+
+ build_name = top_class.__name__.lower() + "-" + platform_name
+ top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
+ soc = top_class(platform, **top_kwargs)
+ soc.finalize()
+ memory_regions = soc.get_memory_regions()
+ csr_regions = soc.get_csr_regions()
+
+ # decode actions
+ action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
+ actions = {k: False for k in action_list}
+ for action in args.action:
+ if action in actions:
+ actions[action] = True
+ else:
+ print("Unknown action: "+action+". Valid actions are:")
+ for a in action_list:
+ print(" "+a)
+ sys.exit(1)
+
+ print("""
+ __ _ __ __ _________
+ / / (_) /____ / / / / __/ _ )
+ / /__/ / __/ -_) /_/ /\ \/ _ |
+ /____/_/\__/\__/\____/___/____/
+
+
+ A small footprint and configurable USB core
+ powered by Migen
+
+====== Building parameters: ======
+System Clk: {} MHz
+===============================""".format(
+ soc.clk_freq/1000000))
+
+ # dependencies
+ if actions["all"]:
+ actions["build-csr-csv"] = True
+ actions["build-bitstream"] = True
+ actions["load-bitstream"] = True
+
+ if actions["build-bitstream"]:
+ actions["build-csr-csv"] = True
+ actions["build-bitstream"] = True
+ actions["load-bitstream"] = True
+
+ if actions["clean"]:
+ subprocess.call(["rm", "-rf", "build/*"])
+
+ if actions["build-csr-csv"]:
+ csr_csv = cpuif.get_csr_csv(csr_regions)
+ write_to_file(args.csr_csv, csr_csv)
+
+ if actions["build-bitstream"]:
+ vns = platform.build(soc, build_name=build_name, run=True)
+ if hasattr(soc, "do_exit") and vns is not None:
+ if hasattr(soc.do_exit, '__call__'):
+ soc.do_exit(vns)
+
+ if actions["load-bitstream"]:
+ prog = platform.create_programmer()
+ prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
--- /dev/null
+from migen.bank.description import *
+from migen.genlib.io import CRG
+from migen.actorlib.fifo import SyncFIFO
+
+from misoclib.soc import SoC
+
+from misoclib.com.liteusb.common import *
+from misoclib.com.liteusb.phy.ft245 import FT245PHY
+from misoclib.com.liteusb.core import LiteUSBCore
+from misoclib.com.liteusb.frontend.wishbone import LiteUSBWishboneBridge
+
+from misoclib.com.gpio import GPIOOut
+
+class LiteUSBSoC(SoC, AutoCSR):
+ csr_map = {}
+ csr_map.update(SoC.csr_map)
+
+ usb_map = {
+ "bridge": 0
+ }
+
+ def __init__(self, platform):
+ clk_freq = int((1/(platform.default_clk_period))*1000000000)
+ SoC.__init__(self, platform, clk_freq,
+ cpu_type="none",
+ with_csr=True, csr_data_width=32,
+ with_uart=False,
+ with_identifier=True,
+ with_timer=False
+ )
+ self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
+ self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
+ self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
+
+
+ # Wishbone Bridge
+ usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
+ self.add_cpu_or_bridge(LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
+ self.add_wb_master(self.cpu_or_bridge.wishbone)
+
+ # Leds
+ leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
+ self.submodules.leds = GPIOOut(leds)
+
+default_subtarget = LiteUSBSoC
projects / litex.git / commitdiff