CPU: Eliminate the hwrei function.

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 7dc02a611e06c6bf8e87ef4b1bd803ca85a99f0c..eefe86bfffd478c45a852a882145e7fc4911047d 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -552,23 +552,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
 
 using namespace AlphaISA;
 
-Fault
-SimpleThread::hwrei()
-{
-    if (!(readPC() & 0x3))
-        return new UnimplementedOpcodeFault;
-
-    setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
-
-    if (!misspeculating()) {
-        if (kernelStats)
-            kernelStats->hwrei();
-    }
-
-    // FIXME: XXX check for interrupts? XXX
-    return NoFault;
-}
-
 /**
  * Check for special simulator handling of specific PAL calls.
  * If return value is false, actual PAL call will be suppressed.

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 270940df2e1c806c38ed7071fe647417ac0969d5..8025ba69f8b436ed170c35d36be784ec4509b53d 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -786,7 +786,16 @@ decode OPCODE default Unknown::unknown() {
     format BasicOperate {
         0x1e: decode PALMODE {
             0: OpcdecFault::hw_rei();
-            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
+            1: hw_rei({{
+                NPC = ExcAddr;
+                ThreadContext * tc = xc->tcBase();
+                if (!tc->misspeculating()) {
+                    AlphaISA::Kernel::Statistics * kernelStats =
+                        tc->getKernelStats();
+                    if (kernelStats)
+                        kernelStats->hwrei();
+                }
+            }}, IsSerializing, IsSerializeBefore);
         }
 
         // M5 special opcodes use the reserved 0x01 opcode space

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 5231712c8eccd6e98bfdc09a70be6fabb26d3019..07898269702e3bd22fcbea18a220bf9ee60d3095 100644 (file)
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -69,6 +69,7 @@ output exec {{
 #include <math.h>
 
 #if FULL_SYSTEM
+#include "arch/alpha/kernel_stats.hh"
 #include "sim/pseudo_inst.hh"
 #endif
 #include "arch/alpha/ipr.hh"
@@ -187,6 +188,7 @@ def operands {{
     'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
     'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
     'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
+    'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5b3c4582c9b0e4622b74b8c1d3447879a69dcbc3..b234bf23fd8259bc222bc0b22fd34040bda257b7 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -336,7 +336,6 @@ class CheckerCPU : public BaseCPU
     void translateDataReadReq(Request *req);
 
 #if FULL_SYSTEM
-    Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 2b9fe4bcf11dbda86990f85be8c7b604041a8d59..93192246cc4814679a24ec39a54a9af07253d792 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -144,10 +144,6 @@ class ExecContext {
     void writeHint(Addr addr, int size, unsigned flags);
 
 #if FULL_SYSTEM
-    /** Somewhat Alpha-specific function that handles returning from
-     * an error or interrupt. */
-    Fault hwrei();
-
     /**
      * Check for special simulator handling of specific PAL calls.  If
      * return value is false, actual PAL call will be suppressed.

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index eb1115565660e93fdd00b7945938743ba28c59b9..174f4a98d0be3e8b637aca7d9b39931b8b9bfae2 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -905,21 +905,6 @@ FullO3CPU<Impl>::post_interrupt(int int_num, int index)
     }
 }
 
-template <class Impl>
-Fault
-FullO3CPU<Impl>::hwrei(unsigned tid)
-{
-#if THE_ISA == ALPHA_ISA
-    // Need to clear the lock flag upon returning from an interrupt.
-    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
-
-    this->thread[tid]->kernelStats->hwrei();
-
-    // FIXME: XXX check for interrupts? XXX
-#endif
-    return NoFault;
-}
-
 template <class Impl>
 bool
 FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 406d965bec6d5d1f21bcaaa95a09eced2bd19783..cdc1d2e588662a520ea671e00888ec49a1a15f94 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -414,9 +414,6 @@ class FullO3CPU : public BaseO3CPU
     /** Posts an interrupt. */
     void post_interrupt(int int_num, int index);
 
-    /** HW return from error interrupt. */
-    Fault hwrei(unsigned tid);
-
     bool simPalCheck(int palFunc, unsigned tid);
 
     /** Returns the Fault for any valid interrupt. */

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 292547b6b87690ec7f4eda572e6fcde980efbfa0..ce59d802be93cc7ff398cf9fcc3ebf9161845b38 100644 (file)
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -168,8 +168,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
 
 #if FULL_SYSTEM
-    /** Calls hardware return from error interrupt. */
-    Fault hwrei();
     /** Traps to handle specified fault. */
     void trap(Fault fault);
     bool simPalCheck(int palFunc);

diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 6398a3afee8c9d9892c3bb860697b8a624ca6ab3..f85527f225112942929dd9af4f820148f40cf0f8 100644 (file)
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -124,28 +124,6 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
 }
 
 #if FULL_SYSTEM
-template <class Impl>
-Fault
-BaseO3DynInst<Impl>::hwrei()
-{
-#if THE_ISA == ALPHA_ISA
-    // Can only do a hwrei when in pal mode.
-    if (!(this->readPC() & 0x3))
-        return new AlphaISA::UnimplementedOpcodeFault;
-
-    // Set the next PC based on the value of the EXC_ADDR IPR.
-    this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
-                                           this->threadNumber));
-
-    // Tell CPU to clear any state it needs to if a hwrei is taken.
-    this->cpu->hwrei(this->threadNumber);
-#else
-
-#endif
-    // FIXME: XXX check for interrupts? XXX
-    return NoFault;
-}
-
 template <class Impl>
 void
 BaseO3DynInst<Impl>::trap(Fault fault)

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c3ea3367340fa4d0e2ff0f16a63d1d97954367e9..e95accdfd7208050dd13c270717e31756ca3c739 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -510,7 +510,6 @@ class OzoneCPU : public BaseCPU
     void dumpInsts() { frontEnd->dumpInsts(); }
 
 #if FULL_SYSTEM
-    Fault hwrei();
     bool simPalCheck(int palFunc);
     void processInterrupts();
 #else

diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index ceb980d4c770091cbb0d406c37c2a953646f3d2b..eb7b1a13f2c93e3a4228592c0f00e7fb07e67b6f 100644 (file)
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -668,21 +668,6 @@ OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
     }
 }
 #else
-template <class Impl>
-Fault
-OzoneCPU<Impl>::hwrei()
-{
-    // Need to move this to ISA code
-    // May also need to make this per thread
-
-    lockFlag = false;
-    lockAddrList.clear();
-    thread.kernelStats->hwrei();
-
-    // FIXME: XXX check for interrupts? XXX
-    return NoFault;
-}
-
 template <class Impl>
 void
 OzoneCPU<Impl>::processInterrupts()

diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index e138cbe13a5da5c2f838673a3a0fbd014531765b..deade93974afca1d10a3eeb4bee869a26254ac5a 100644 (file)
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -240,7 +240,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
     void setMiscReg(int misc_reg, const MiscReg &val);
 
 #if FULL_SYSTEM
-    Fault hwrei();
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
 #else

diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 8519917f5accb0a00a390f56ad628583ff4ead92..8fc5077a64e210fd6799a52ae98f6cb094675ee0 100644 (file)
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -248,21 +248,6 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 
 #if FULL_SYSTEM
 
-template <class Impl>
-Fault
-OzoneDynInst<Impl>::hwrei()
-{
-    if (!(this->readPC() & 0x3))
-        return new AlphaISA::UnimplementedOpcodeFault;
-
-    this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
-
-    this->cpu->hwrei();
-
-    // FIXME: XXX check for interrupts? XXX
-    return NoFault;
-}
-
 template <class Impl>
 void
 OzoneDynInst<Impl>::trap(Fault fault)

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b7fcf1708df123c1ffbf1d6bb24581de6039f352..b28a690bb3ef618d04bb3cce0ca978118a4ad001 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -413,7 +413,6 @@ class BaseSimpleCPU : public BaseCPU
     //Fault CacheOp(uint8_t Op, Addr EA);
 
 #if FULL_SYSTEM
-    Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 377bfcd796e60663724bffdebc99154639e39946..89d5ba99fc2dec7c8e453018c03487ee49fc1dc9 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -185,8 +185,6 @@ class SimpleThread : public ThreadState
 
     void dumpFuncProfile();
 
-    Fault hwrei();
-
     bool simPalCheck(int palFunc);
 
 #endif