add sv.bc vlset-inverted test

this one inverts all the logic (some instead of all, LE instead of GT,
VL-truncate if FAIL)
and thus can swap the success-fail branch point.  avoids one branch in loops

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index 94adc6e536484386d0c9c8964afdefaf8e8eb273..afd8ba605e977265ba740b4d0183e48fdf4e7cdb 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -134,6 +134,37 @@ class DecoderTestCase(FHDLTestCase):
                 print ("SVSTATE.vl", bin(svstate.vl))
                 self.assertEqual(svstate.vl, i-7)
 
+    def test_sv_branch_cond_vlset_inv(self):
+        for i in [7, 8, 9]:
+            lst = SVP64Asm(
+                [f"addi 1, 0, {i+1}",  # set r1 to i
+                 f"addi 2, 0, {i}",  # set r2 to i
+                "cmpi cr0, 1, 1, 8",  # compare r1 with 8 and store to cr0
+                "cmpi cr1, 1, 2, 8",  # compare r2 with 8 and store to cr1
+                "sv.bc/vsb 4, *1, 0xc", # bgt 0xc - branch if BOTH
+                                       # r1 AND r2 greater 8 to the nop below
+                                       # also truncate VL at the fail-point
+                "addi 3, 0, 0x1234",   # if tests fail this shouldn't execute
+                "or 0, 0, 0"]          # branch target
+                )
+            lst = list(lst)
+
+            # SVSTATE (in this case, VL=2)
+            svstate = SVP64State()
+            svstate.vl = 2 # VL
+            svstate.maxvl = 2 # MAXVL
+            print ("SVSTATE", bin(svstate.asint()))
+
+            with self.subTest("vlset_inv %d" % i):
+                with Program(lst, bigendian=False) as program:
+                    sim = self.run_tst_program(program, svstate=svstate)
+                    print ("SVSTATE.vl", bin(svstate.vl))
+                    if i == 9:
+                        self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+                    else:
+                        self.assertEqual(svstate.vl, 0)
+                    self.assertEqual(svstate.vl, i-7)
+
     def test_sv_branch_ctr(self):
         """XXX under development, seems to be good.
         basically this will reduce CTR under a *vector* loop, where BO[0]
@@ -205,7 +236,7 @@ class DecoderTestCase(FHDLTestCase):
             # MAXVL repeatedly subtracted from VL (r1), last loop has remainder
             self.assertEqual(sim.gpr(1), SelectableInt(target % maxvl, 64))
 
-    def tst_sv_add_cr(self):
+    def norun_sv_add_cr(self):
         """>>> lst = ['sv.add. *1, *5, *9'
                        ]