S/390: Add widening vector mult lo/hi patterns

Add support for widening vector multiply lo/hi patterns.  These do not
directly match on IBM Z instructions but can be emulated with even/odd
+ vector merge.

gcc/ChangeLog:

2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/vector.md ("vec_widen_umult_lo_<mode>")
	("vec_widen_umult_hi_<mode>", "vec_widen_smult_lo_<mode>")
	("vec_widen_smult_hi_<mode>"): New expander definitions.

From-SVN: r253192

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5e7f82dc2c4e4152e428d35b8c416b2435e8a278..9df1ff54470cc515d0c8f7343cea191454fbe3b8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+       * config/s390/vector.md ("vec_widen_umult_lo_<mode>")
+       ("vec_widen_umult_hi_<mode>", "vec_widen_smult_lo_<mode>")
+       ("vec_widen_smult_hi_<mode>"): New expander definitions.
+
 2017-09-26  Richard Earnshaw  <rearnsha@arm.com>
 
        PR target/82175

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 3cf79896720cba6eba831cf961ca3564a2317ed1..29131cdbf359f5fa7e984c7f6fbad864953b90d5 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -1065,10 +1065,85 @@
   "vmlo<bhfgq>\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
-; vec_widen_umult_hi
-; vec_widen_umult_lo
-; vec_widen_smult_hi
-; vec_widen_smult_lo
+
+; Widening hi/lo multiplications
+
+; The S/390 instructions vml and vmh return the low or high parts of
+; the double sized result elements in the corresponding elements of
+; the target register.  That's NOT what the vec_widen_umult_lo/hi
+; patterns are expected to do.
+
+; We emulate the widening lo/hi multiplies with the even/odd versions
+; followed by a vector merge
+
+
+(define_expand "vec_widen_umult_lo_<mode>"
+  [(set (match_dup 3)
+       (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+                             (match_operand:VI_QHS 2 "register_operand"  "v")]
+                            UNSPEC_VEC_UMULT_EVEN))
+   (set (match_dup 4)
+       (unspec:<vec_double> [(match_dup 1) (match_dup 2)]
+                            UNSPEC_VEC_UMULT_ODD))
+   (set (match_operand:<vec_double>                 0 "register_operand" "=v")
+       (unspec:<vec_double> [(match_dup 3) (match_dup 4)]
+                            UNSPEC_VEC_MERGEL))]
+  "TARGET_VX"
+ {
+   operands[3] = gen_reg_rtx (<vec_double>mode);
+   operands[4] = gen_reg_rtx (<vec_double>mode);
+ })
+
+(define_expand "vec_widen_umult_hi_<mode>"
+  [(set (match_dup 3)
+       (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+                             (match_operand:VI_QHS 2 "register_operand"  "v")]
+                            UNSPEC_VEC_UMULT_EVEN))
+   (set (match_dup 4)
+       (unspec:<vec_double> [(match_dup 1) (match_dup 2)]
+                            UNSPEC_VEC_UMULT_ODD))
+   (set (match_operand:<vec_double>                 0 "register_operand" "=v")
+       (unspec:<vec_double> [(match_dup 3) (match_dup 4)]
+                            UNSPEC_VEC_MERGEH))]
+  "TARGET_VX"
+ {
+   operands[3] = gen_reg_rtx (<vec_double>mode);
+   operands[4] = gen_reg_rtx (<vec_double>mode);
+ })
+
+(define_expand "vec_widen_smult_lo_<mode>"
+  [(set (match_dup 3)
+       (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+                             (match_operand:VI_QHS 2 "register_operand"  "v")]
+                            UNSPEC_VEC_SMULT_EVEN))
+   (set (match_dup 4)
+       (unspec:<vec_double> [(match_dup 1) (match_dup 2)]
+                            UNSPEC_VEC_SMULT_ODD))
+   (set (match_operand:<vec_double>                 0 "register_operand" "=v")
+       (unspec:<vec_double> [(match_dup 3) (match_dup 4)]
+                            UNSPEC_VEC_MERGEL))]
+  "TARGET_VX"
+ {
+   operands[3] = gen_reg_rtx (<vec_double>mode);
+   operands[4] = gen_reg_rtx (<vec_double>mode);
+ })
+
+(define_expand "vec_widen_smult_hi_<mode>"
+  [(set (match_dup 3)
+       (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+                             (match_operand:VI_QHS 2 "register_operand"  "v")]
+                            UNSPEC_VEC_SMULT_EVEN))
+   (set (match_dup 4)
+       (unspec:<vec_double> [(match_dup 1) (match_dup 2)]
+                            UNSPEC_VEC_SMULT_ODD))
+   (set (match_operand:<vec_double>                 0 "register_operand" "=v")
+       (unspec:<vec_double> [(match_dup 3) (match_dup 4)]
+                            UNSPEC_VEC_MERGEH))]
+  "TARGET_VX"
+ {
+   operands[3] = gen_reg_rtx (<vec_double>mode);
+   operands[4] = gen_reg_rtx (<vec_double>mode);
+ })
 
 ; vec_widen_ushiftl_hi
 ; vec_widen_ushiftl_lo