alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.

It's no longer used.

Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
Reviewed-on: https://gem5-review.googlesource.com/6826
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index f1c39cb05324aac8726d7cebcb2c4c09b239884b..54b8003becac4465f013b09e98bef3178aa5b544 100644 (file)
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -111,10 +111,6 @@ enum mode_type
 
 const int MachineBytes = 8;
 
-// return a no-op instruction... used for instruction fetch faults
-// Alpha UNOP (ldq_u r31,0(r0))
-const ExtMachInst NoopMachInst = 0x2ffe0000;
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
 

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 8be2bf04ab325d7f3161fa6c7a46f2f8e232dc9e..fa2779558e42ba3e81ca04ddba1673ffbd26c8d6 100644 (file)
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -96,9 +96,6 @@ namespace ArmISA
     // Max. physical address range in bits supported by the architecture
     const unsigned MaxPhysAddrRange = 48;
 
-    // return a no-op instruction... used for instruction fetch faults
-    const ExtMachInst NoopMachInst = 0x01E320F000ULL;
-
     const int MachineBytes = 4;
 
     const uint32_t HighVecs = 0xFFFF0000;

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index ca375f2e859a284b1543434db5f9f2dee585fd66..7a1607183af850bdf00d88edf880b1392cdb0829 100644 (file)
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -142,9 +142,6 @@ enum mode_type
     mode_number             // number of modes
 };
 
-// return a no-op instruction... used for instruction fetch faults
-const ExtMachInst NoopMachInst = 0x00000000;
-
 const int ANNOTE_NONE = 0;
 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 

diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 3abc831ff7330f1f101e30ccdce4bcfa0563a28b..41a8d7d1bcd9742a3fb1f4bce9b17f4f5c1088e4 100644 (file)
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -63,9 +63,6 @@ const Addr PteMask = NPtePage - 1;
 
 const int MachineBytes = 4;
 
-// This is ori 0, 0, 0
-const ExtMachInst NoopMachInst = 0x60000000;
-
 // Memory accesses can be unaligned
 const bool HasUnalignedMemAcc = true;
 

diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 327d644983f50b884baf91ee7b629968f1377f7e..21e684a25836978027c9dfe82676dbd032f05780 100644 (file)
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -63,8 +63,6 @@ using namespace LittleEndianGuest;
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 
-const ExtMachInst NoopMachInst = 0x00000013;
-
 // Memory accesses can be unaligned (at least for double-word memory accesses)
 const bool HasUnalignedMemAcc = true;
 

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index b9253863e8eb30c70eea14c534a0f5315f59f712..4f98f7580205b802f008e6e15b042fae40923cca 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -47,9 +47,6 @@ using namespace BigEndianGuest;
 // SPARC has a delay slot
 #define ISA_HAS_DELAY_SLOT 1
 
-// SPARC NOP (sethi %(hi(0), g0)
-const MachInst NoopMachInst = 0x01000000;
-
 // real address virtual mapping
 // sort of like alpha super page, but less frequently used
 const Addr SegKPMEnd  = ULL(0xfffffffc00000000);

diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 88cd16eff08a2e91b7c7288b54f2488d544b4fe9..2b19b1ba7cc51d70fc93d6317c2affe6493fa0b2 100644 (file)
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -56,10 +56,6 @@ namespace X86ISA
     // X86 does not have a delay slot
 #define ISA_HAS_DELAY_SLOT 0
 
-    // X86 NOP (XCHG rAX, rAX)
-    //XXX This needs to be set to an intermediate instruction struct
-    //which encodes this instruction
-
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
 
@@ -68,19 +64,6 @@ namespace X86ISA
 
     const bool CurThreadInfoImplemented = false;
     const int CurThreadInfoReg = -1;
-
-    const ExtMachInst NoopMachInst M5_VAR_USED = {
-        0x0,                            // No legacy prefixes.
-        0x0,                            // No rex prefix.
-        0x0,                            // No two / three byte escape sequence
-        { OneByteOpcode, 0x90 },        // One opcode byte, 0x90.
-        0x0, 0x0,                       // No modrm or sib.
-        0, 0,                           // No immediate or displacement.
-        8, 8, 8,                        // All sizes are 8.
-        0,                              // Displacement size is 0.
-        SixtyFourBitMode                // Behave as if we're in 64 bit
-                                        // mode (this doesn't actually matter).
-    };
 }
 
 #endif // __ARCH_X86_ISATRAITS_HH__