abc9_ops: -reintegrate to be sensitive to start_offset too

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 78c90286666e71e2e815374b4f7888e3d441118d..1345188a45992940fc3cf54ac0afc8f3331b82aa 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -741,8 +741,10 @@ void reintegrate(RTLIL::Module *module)
        if (mapped_mod == NULL)
                log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
 
-       for (auto w : mapped_mod->wires())
-               module->addWire(remap_name(w->name), GetSize(w));
+       for (auto w : mapped_mod->wires()) {
+               auto nw = module->addWire(remap_name(w->name), GetSize(w));
+               nw->start_offset = w->start_offset;
+       }
 
        dict<IdString,std::vector<IdString>> box_ports;
 
@@ -989,7 +991,7 @@ void reintegrate(RTLIL::Module *module)
                wire->attributes.erase(ID::abc9_scc);
 
                RTLIL::Wire *remap_wire = module->wire(remap_name(port));
-               RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
+               RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));
                log_assert(GetSize(signal) >= GetSize(remap_wire));
 
                RTLIL::SigSig conn;