Added "equiv_add -cell"

diff --git a/kernel/yosys.h b/kernel/yosys.h
index af849fca821575d61757de4f5dd7b9cc5e36c939..80346a47cf2ab41fa785239ad1d204620034c11a 100644 (file)
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -169,7 +169,6 @@ namespace RTLIL {
        struct IdString;
        struct Const;
        struct SigBit;
-       struct SigChunk;
        struct SigSpec;
        struct Wire;
        struct Cell;
@@ -185,7 +184,6 @@ namespace AST {
 using RTLIL::IdString;
 using RTLIL::Const;
 using RTLIL::SigBit;
-using RTLIL::SigChunk;
 using RTLIL::SigSpec;
 using RTLIL::Wire;
 using RTLIL::Cell;
@@ -244,6 +242,8 @@ YOSYS_NAMESPACE_END
 YOSYS_NAMESPACE_BEGIN
 
 using RTLIL::State;
+using RTLIL::SigChunk;
+using RTLIL::SigSig;
 
 namespace hashlib {
        template<> struct hash_ops<RTLIL::State> : hash_ops<int> {};

diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc
index 4ce750b1dee152adef9820ac65eaa0c4e0403083..7b8ba9058bca9e135e2d5f19a3dd11a056bc4770 100644 (file)
--- a/passes/equiv/equiv_add.cc
+++ b/passes/equiv/equiv_add.cc
@@ -33,56 +33,117 @@ struct EquivAddPass : public Pass {
                log("\n");
                log("This command adds an $equiv cell for the specified signals.\n");
                log("\n");
+               log("\n");
+               log("    equiv_add -cell gold_cell gate_cell\n");
+               log("\n");
+               log("This command adds $equiv cells for the ports of the specified cells.\n");
+               log("\n");
        }
        virtual void execute(std::vector<std::string> args, Design *design)
        {
-               if (GetSize(args) != 3)
-                        cmd_error(args, GetSize(args)-1, "Invalid number of arguments.");
-
                if (design->selected_active_module.empty())
                        log_cmd_error("This command must be executed in module context!\n");
 
                Module *module = design->module(design->selected_active_module);
                log_assert(module != nullptr);
 
-               SigSpec gold_signal, gate_signal;
+               if (GetSize(args) == 4 && args[1] == "-cell")
+               {
+                       Cell *gold_cell = module->cell(RTLIL::escape_id(args[2]));
+                       Cell *gate_cell = module->cell(RTLIL::escape_id(args[3]));
 
-               if (!SigSpec::parse(gate_signal, module, args[2]))
-                       log_cmd_error("Error in gate signal: %s\n", args[2].c_str());
+                       if (gold_cell == nullptr)
+                               log_cmd_error("Can't find gold cell '%s'.\n", args[2].c_str());
 
-               if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1]))
-                       log_cmd_error("Error in gold signal: %s\n", args[1].c_str());
+                       if (gate_cell == nullptr)
+                               log_cmd_error("Can't find gate cell '%s'.\n", args[3].c_str());
 
-               log_assert(GetSize(gold_signal) == GetSize(gate_signal));
-               SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
+                       for (auto conn : gold_cell->connections())
+                       {
+                               auto port = conn.first;
+                               SigSpec gold_sig = gold_cell->getPort(port);
+                               SigSpec gate_sig = gate_cell->getPort(port);
+                               int width = std::min(GetSize(gold_sig), GetSize(gate_sig));
 
-               SigMap sigmap(module);
-               sigmap.apply(gold_signal);
-               sigmap.apply(gate_signal);
+                               if (gold_cell->input(port) && gate_cell->input(port))
+                               {
+                                       SigSpec combined_sig = module->addWire(NEW_ID, width);
 
-               dict<SigBit, SigBit> to_equiv_bits;
-               pool<Cell*> added_equiv_cells;
+                                       for (int i = 0; i < width; i++) {
+                                               module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
+                                               gold_sig[i] = gate_sig[i] = combined_sig[i];
+                                       }
 
-               for (int i = 0; i < GetSize(gold_signal); i++) {
-                       Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
-                       equiv_cell->set_bool_attribute("\\keep");
-                       to_equiv_bits[gold_signal[i]] = equiv_signal[i];
-                       to_equiv_bits[gate_signal[i]] = equiv_signal[i];
-                       added_equiv_cells.insert(equiv_cell);
+                                       gold_cell->setPort(port, gold_sig);
+                                       gate_cell->setPort(port, gate_sig);
+                                       continue;
+                               }
+
+                               if (gold_cell->output(port) && gate_cell->output(port))
+                               {
+                                       SigSpec new_gold_wire = module->addWire(NEW_ID, width);
+                                       SigSpec new_gate_wire = module->addWire(NEW_ID, width);
+                                       SigSig gg_conn;
+
+                                       for (int i = 0; i < width; i++) {
+                                               module->addEquiv(NEW_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]);
+                                               gg_conn.first.append(gate_sig[i]);
+                                               gg_conn.second.append(gold_sig[i]);
+                                               gold_sig[i] = new_gold_wire[i];
+                                               gate_sig[i] = new_gate_wire[i];
+                                       }
+
+                                       module->connect(gg_conn);
+                                       gold_cell->setPort(port, gold_sig);
+                                       gate_cell->setPort(port, gate_sig);
+                                       continue;
+                               }
+                       }
                }
+               else
+               {
+                       if (GetSize(args) != 3)
+                                cmd_error(args, GetSize(args)-1, "Invalid number of arguments.");
 
-               for (auto cell : module->cells())
-               for (auto conn : cell->connections())
-                       if (!added_equiv_cells.count(cell) && cell->input(conn.first)) {
-                               SigSpec new_sig;
-                               for (auto bit : conn.second)
-                                       if (to_equiv_bits.count(sigmap(bit)))
-                                               new_sig.append(to_equiv_bits.at(sigmap(bit)));
-                                       else
-                                                new_sig.append(bit);
-                               if (conn.second != new_sig)
-                                       cell->setPort(conn.first, new_sig);
+                       SigSpec gold_signal, gate_signal;
+
+                       if (!SigSpec::parse(gate_signal, module, args[2]))
+                               log_cmd_error("Error in gate signal: %s\n", args[2].c_str());
+
+                       if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1]))
+                               log_cmd_error("Error in gold signal: %s\n", args[1].c_str());
+
+                       log_assert(GetSize(gold_signal) == GetSize(gate_signal));
+                       SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
+
+                       SigMap sigmap(module);
+                       sigmap.apply(gold_signal);
+                       sigmap.apply(gate_signal);
+
+                       dict<SigBit, SigBit> to_equiv_bits;
+                       pool<Cell*> added_equiv_cells;
+
+                       for (int i = 0; i < GetSize(gold_signal); i++) {
+                               Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
+                               equiv_cell->set_bool_attribute("\\keep");
+                               to_equiv_bits[gold_signal[i]] = equiv_signal[i];
+                               to_equiv_bits[gate_signal[i]] = equiv_signal[i];
+                               added_equiv_cells.insert(equiv_cell);
                        }
+
+                       for (auto cell : module->cells())
+                       for (auto conn : cell->connections())
+                               if (!added_equiv_cells.count(cell) && cell->input(conn.first)) {
+                                       SigSpec new_sig;
+                                       for (auto bit : conn.second)
+                                               if (to_equiv_bits.count(sigmap(bit)))
+                                                       new_sig.append(to_equiv_bits.at(sigmap(bit)));
+                                               else
+                                                        new_sig.append(bit);
+                                       if (conn.second != new_sig)
+                                               cell->setPort(conn.first, new_sig);
+                               }
+               }
        }
 } EquivAddPass;