opcodes/

	* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
	(powerpc_operands <SPRG>): Call the above.  Bit field is 5 bits.
	(SPRG_MASK): Delete.
	(XSPRG_MASK): Mask off extra bits now part of sprg field.
        (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask.  Move
	mfsprg4..7 after msprg and consolidate.

gas/testsuite
	* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
	* gas/ppc/booke.d: Likewise.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 733d5d7bde102b7c9bcf7ebc26fd89afd867a904..e35eba6a1157ed6c51e9a5dc1a45810a92b56b7c 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2005-03-10  Jeff Baker  <jbaker@qnx.com>
+           Alan Modra  <amodra@bigpond.net.au>
+
+       * gas/ppc/booke.s: Add new m[t,f]sprg testcases.
+       * gas/ppc/booke.d: Likewise.
+
 2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
 
        * gas/mips/vr4130.[sd]: New test.
@@ -93,12 +99,11 @@
 
 2005-03-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
 
-       * gas/arc/extensions.s: Add tests for extcoreregister
-       * gas/arc/extensions.d: Likewise.  
-       * gas/arc/warn.s: Warnings for readonly core registers
-       accessed .
-       * gas/arc/warn.d:Likewise.
-       * testsuite/gas/arc/arc.exp:Run extensions testcase.
+       * gas/arc/extensions.s: Add tests for extcoreregister.
+       * gas/arc/extensions.d: Likewise.
+       * gas/arc/warn.s: Warnings for readonly core registers accessed.
+       * gas/arc/warn.d: Likewise.
+       * testsuite/gas/arc/arc.exp: Run extensions testcase.
 
 2005-03-03  Richard Sandiford  <rsandifo@redhat.com>
 
@@ -106,8 +111,8 @@
 
 2005-03-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
 
-       * gas/arc/ld.s:Add checks for short immediates with ld
-       * gas/arc/ld.d:Likewise. 
+       * gas/arc/ld.s: Add checks for short immediates with ld.
+       * gas/arc/ld.d: Likewise.
 
 2005-03-02  Daniel Jacobowitz  <dan@codesourcery.com>
 

diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d
index b1327497c12de811dd96e7816ab08f2f2c372cc6..0f92aecf0e07eb844100a016bf8890c6c80d0c71 100644 (file)
--- a/gas/testsuite/gas/ppc/booke.d
+++ b/gas/testsuite/gas/ppc/booke.d
@@ -142,3 +142,11 @@ Disassembly of section \.text:
  1c0:  7c 00 06 ac     mbar    
  1c4:  7c 00 06 ac     mbar    
  1c8:  7c 20 06 ac     mbar    1
+ 1cc:  7c 12 42 a6     mfsprg  r0,2
+ 1d0:  7c 12 42 a6     mfsprg  r0,2
+ 1d4:  7c 12 43 a6     mtsprg  2,r0
+ 1d8:  7c 12 43 a6     mtsprg  2,r0
+ 1dc:  7c 07 42 a6     mfsprg  r0,7
+ 1e0:  7c 07 42 a6     mfsprg  r0,7
+ 1e4:  7c 17 43 a6     mtsprg  7,r0
+ 1e8:  7c 17 43 a6     mtsprg  7,r0

diff --git a/gas/testsuite/gas/ppc/booke.s b/gas/testsuite/gas/ppc/booke.s
index 4c40b498ebe2f7c03ee10d71885077cbb3dd1474..0c6cf88f66a418d2642f15d497b00889c9d73ef5 100644 (file)
--- a/gas/testsuite/gas/ppc/booke.s
+++ b/gas/testsuite/gas/ppc/booke.s
@@ -134,3 +134,12 @@ branch_target_8:
        mbar
        mbar    0
        mbar    1
+
+       mfsprg 0, 2
+       mfsprg2 0
+       mtsprg 2, 0
+       mtsprg2 0
+       mfsprg 0, 7
+       mfsprg7 0
+       mtsprg 7, 0
+       mtsprg7 0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 405937f254a69a373331963ab968deb2b9ac868d..7e3bbf55823d6a14c4dab70de94aa5117940afa5 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2005-03-10  Jeff Baker  <jbaker@qnx.com>
+           Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
+       (powerpc_operands <SPRG>): Call the above.  Bit field is 5 bits.
+       (SPRG_MASK): Delete.
+       (XSPRG_MASK): Mask off extra bits now part of sprg field.
+        (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask.  Move
+       mfsprg4..7 after msprg and consolidate.
+
 2005-03-09  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
 
        * vax-dis.c (entry_mask_bit): New array.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 68f73d23bad083a69582295fda95a8bc91f90045..bf1796fabb6d23891e35c673ff92b05ab0c395da 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -84,6 +84,8 @@ static unsigned long insert_sh6 (unsigned long, long, int, const char **);
 static long extract_sh6 (unsigned long, int, int *);
 static unsigned long insert_spr (unsigned long, long, int, const char **);
 static long extract_spr (unsigned long, int, int *);
+static unsigned long insert_sprg (unsigned long, long, int, const char **);
+static long extract_sprg (unsigned long, int, int *);
 static unsigned long insert_tbr (unsigned long, long, int, const char **);
 static long extract_tbr (unsigned long, int, int *);
 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
@@ -465,8 +467,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 #define SPRG SPRBAT + 1
-#define SPRG_MASK (0x3 << 16)
-  { 2, 16, NULL, NULL, 0 },
+  { 5, 16, insert_sprg, extract_sprg, 0 },
 
   /* The SR field in an X form instruction.  */
 #define SR SPRG + 1
@@ -1397,6 +1398,47 @@ extract_spr (unsigned long insn,
   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
 }
 
+/* Some dialects have 8 SPRG registers instead of the standard 4.  */
+
+static unsigned long
+insert_sprg (unsigned long insn,
+            long value,
+            int dialect,
+            const char **errmsg)
+{
+  /* This check uses PPC_OPCODE_403 because PPC405 is later defined
+     as a synonym.  If ever a 405 specific dialect is added this
+     check should use that instead.  */
+  if (value > 7
+      || (value > 3
+         && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
+    *errmsg = _("invalid sprg number");
+
+  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
+     user mode.  Anything else must use spr 272..279.  */
+  if (value <= 3 || (insn & 0x100) != 0)
+    value |= 0x10;
+
+  return insn | ((value & 0x17) << 16);
+}
+
+static long
+extract_sprg (unsigned long insn,
+             int dialect,
+             int *invalid)
+{
+  unsigned long val = (insn >> 16) & 0x1f;
+
+  /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
+     If not BOOKE or 405, then both use only 272..275.  */
+  if (val <= 3
+      || (val < 0x10 && (insn & 0x100) != 0)
+      || (val - 0x10 > 3
+         && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
+    *invalid = 1;
+  return val & 7;
+}
+
 /* The TBR field in an XFX instruction.  This is just like SPR, but it
    is optional.  When TBR is omitted, it must be inserted as 268 (the
    magic number of the TB register).  These functions treat 0
@@ -1705,7 +1747,7 @@ extract_tbr (unsigned long insn,
 
 /* An XFX form instruction with the SPR field filled in except for the
    SPRG field.  */
-#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
+#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
 
 /* An X form instruction with everything filled in except the E field.  */
 #define XE_MASK (0xffff7fff)
@@ -3677,25 +3719,21 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,  { RT } },
 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,  { RT } },
 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
-{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,  { RT } },
-{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, BOOKE,   { RT } },
-{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,  { RT } },
-{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, BOOKE,   { RT } },
-{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,  { RT } },
-{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, BOOKE,   { RT } },
-{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,  { RT } },
-{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, BOOKE,   { RT } },
 { "mftb",       X(31,371),        X_MASK,    CLASSIC,  { RT, TBR } },
 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC, { RT } },
 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC, { RT } },
 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
-{ "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,    { RT, SPRG } },
+{ "mfsprg",     XSPR(31,339,256),  XSPRG_MASK, PPC,    { RT, SPRG } },
 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,     { RT } },
 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,     { RT } },
 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,     { RT } },
 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405 | BOOKE,  { RT } },
+{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405 | BOOKE,  { RT } },
+{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405 | BOOKE,  { RT } },
+{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405 | BOOKE,  { RT } },
 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,   { RT } },
 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,     { RT } },
 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
@@ -3998,7 +4036,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,   { RS } },
 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,   { RS } },
 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
-{ "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,      { SPRG, RS } },
+{ "mtsprg",    XSPR(31,467,256),  XSPRG_MASK,PPC,      { SPRG, RS } },
 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,      { RS } },
 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,      { RS } },
 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,      { RS } },