+2019-07-02 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/mmx.md (mmx_pack<s_trunsuffix>swb):
+ Use TARGET_SSE2 && SSE_REGNO_P in split condition.
+ (mmx_packssdw): Ditto.
+ (mmx_punpckhbw): Ditto.
+ (mmx_punpcklbw): Ditto.
+ (mmx_punpckhwd): Ditto.
+ (mmx_punpcklwd): Ditto.
+ (mmx_punpckhdq): Ditto.
+ (mmx_punpckldq): Ditto.
+ (*vec_dupv4hi): Ditto.
+ (*vec_dupv2si): Ditto.
+ (mmx_pmovmskb): Ditto.
+ * config/i386/sse.md (sse_cvtpi2ps): Use
+ TARGET_SSE2 && SSE_REG_P in split condition.
+ (ssse3_ph<plusminus_mnemonic>wv4hi3): Use
+ TARGET_SSSE3 && SSE_REGNO_P in split condition.
+ (ssse3_ph<plusminus_mnemonic>dv2si3): Ditto.
+ (ssse3_pshufbv8qi3): Ditto.
+ (ssse3_palignrdi): Ditto.
+
2019-07-02 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn.md (movdi_symbol_save_scc): Convert to define_insn
pack<s_trunsuffix>swb\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_pack (operands, <any_s_truncate:CODE>); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
packssdw\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
punpckhbw\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, true); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
punpcklbw\t{%2, %0|%0, %k2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, false); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
punpckhwd\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, true); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
punpcklwd\t{%2, %0|%0, %k2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, false); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
punpckhdq\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, true); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
punpckldq\t{%2, %0|%0, %k2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, false); DONE;"
[(set_attr "mmx_isa" "native,sse_noavx,avx")
pshufw\t{$0, %0, %0|%0, %0, 0}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
{
rtx op;
"@
pmovmskb\t{%1, %0|%0, %1}
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 0)
(unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
(set (match_dup 0)
cvtpi2ps\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE2 && reload_completed
+ && SSE_REG_P (operands[2])"
[(const_int 0)]
{
rtx op2 = lowpart_subreg (V4SImode, operands[2],
ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSSE3 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
{
/* Generate SSE version of the operation. */
ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSSE3 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
{
/* Generate SSE version of the operation. */
pshufb\t{%2, %0|%0, %2}
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSSE3 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 3) (match_dup 5))
(set (match_dup 3)
(and:V4SI (match_dup 3) (match_dup 2)))
gcc_unreachable ();
}
}
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSSE3 && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 0)
(lshiftrt:V1TI (match_dup 0) (match_dup 3)))]
{