(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index b7999c11e1c296d3531bcf28862436650c1bd8e8..303356e25aae4b8ff4fe92600e08a4aecd9eacf3 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -50,11 +50,12 @@ The Mode table for Arithmetic and Logical operations
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
-| 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
+| 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
 Fields:
 
 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
+* **zz**: both sz and dz are set equal to this flag
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1