-In this directory you will find out, how to generate a spice output
-operating in two modes, analog or event-driven mode supported by ngspice
-xspice sub-module.
+In this directory contains an example for generating a spice output using two
+different spice modes, normal analog transient simulation and event-driven
+digital simulation as supported by ngspice xspice sub-module.
Each test bench can be run separately by either running:
- testbench_digital.sh for mixed-signal digital simulation.
The later case also includes pure verilog simulation using the iverilog
-and gtkwave to represent the results.
+and gtkwave for comparison.
+
#!/bin/bash
+set -ex
+
# iverlog simulation
echo "Doing Verilog simulation with iverilog"
-iverilog -o dsn counter.v counter_tb.v
-./dsn -lxt2
-gtkwave counter_tb.vcd &
+iverilog -o counter_tb counter.v counter_tb.v
+./counter_tb; gtkwave counter_tb.gtkw &
# yosys synthesis
-set -ex
-
../../yosys counter_digital.ys
# requires ngspice with xspice support enabled:
ngspice testbench_digital.sp
+