(no commit message)

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index a6b421f71aedd1b2e177be234933e5dc489b7327..7223f89a2280977964061838600646f4849e8509 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -275,10 +275,10 @@ uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
 }
 ```
 
-For SVP64 these use EXTRA2 and allow Twin Elwidths. The reason is so
-that the Register used as an Accumulator (RS) may have its own
-Element Width Override. This allows e.g. a 16 bit accumulator for 8 bit
-differences.
+For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
+differences.  Form is `RM-1P-3S1D` where RS-as-source has a separate
+SVP64 designation from RS-as-dest. This gives a limited range of
+non-overwrite capability.
 
 # shift-and-add