bus: 14-bit CSR addresses

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 297bd4e4f6d14413ebdc2507a55e30b2c0e35f6b..667d58b83a7e4cf8602f14844c2e8e0ffad093ed 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -2,7 +2,7 @@ from migen.fhdl import structure as f
 from .simple import Simple
 
 _desc = [
-       (True,  "a",    16),
+       (True,  "a",    14),
        (True,  "we",   1),
        (True,  "d",    32),
        (False, "d",    32)

diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
index 6d0099042875b438c5db953f94c9290638373a5c..9c0a4c24ff203567957eccee9f11919c19c34c2c 100644 (file)
--- a/migen/bus/wishbone2csr.py
+++ b/migen/bus/wishbone2csr.py
@@ -14,7 +14,7 @@ class Inst():
                sync = [
                        f.Assign(self.csr.we_o, self.wishbone.we_i),
                        f.Assign(self.csr.d_o, self.wishbone.dat_i),
-                       f.Assign(self.csr.a_o, self.wishbone.adr_i[:16]),
+                       f.Assign(self.csr.a_o, self.wishbone.adr_i[2:16]),
                        f.Assign(self.wishbone.ack_o, 0),
                        f.Assign(self.wishbone.dat_o, self.csr.d_i)
                ]