[AArch64_BE 2/4] Big-Endian lane numbering fix

2013-01-23  Alex Velenko  <Alex.Velenko@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_be_checked_get_lane<mode>): New define_expand.
	* config/aarch64/aarch64-simd-builtins.def
	(BUILTIN_VALL (GETLANE, be_checked_get_lane, 0):
	New builtin definition.
	* config/aarch64/arm_neon.h: (__aarch64_vget_lane_any):
	Use new safe be builtin.

From-SVN: r206970

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 28e41625f04303e284028d9f898d396ffd18f6d7..1670683f9e8a05168a2c20030f9176bc84558eea 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-01-23  Alex Velenko  <Alex.Velenko@arm.com>
+
+       * config/aarch64/aarch64-simd.md
+       (aarch64_be_checked_get_lane<mode>): New define_expand.
+       * config/aarch64/aarch64-simd-builtins.def
+       (BUILTIN_VALL (GETLANE, be_checked_get_lane, 0):
+       New builtin definition.
+       * config/aarch64/arm_neon.h: (__aarch64_vget_lane_any):
+       Use new safe be builtin.
+
 2014-01-23  Alex Velenko  <Alex.Velenko@arm.com>
 
        * config/aarch64/aarch64-simd.md (aarch64_be_ld1<mode>):

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 034afbf515eac65c1b2592a3c731cfcceb6a2535..185281ae5e95d54f6854483550629a57f8f9be48 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -49,6 +49,7 @@
 
   BUILTIN_VALL (GETLANE, get_lane, 0)
   VAR1 (GETLANE, get_lane, 0, di)
+  BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
 
   BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
   BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 1454a7e11eab75abd5fc04bd84a2dce4271e952e..14eb7d08d155b252164e19f79de34aaf6a2e715c 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2062,6 +2062,20 @@
   [(set_attr "type" "neon_to_gp<q>")]
 )
 
+(define_expand "aarch64_be_checked_get_lane<mode>"
+  [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand")
+   (match_operand:VALL 1 "register_operand")
+   (match_operand:SI 2 "immediate_operand")]
+  "TARGET_SIMD"
+  {
+    operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+    emit_insn (gen_aarch64_get_lane<mode> (operands[0],
+                                          operands[1],
+                                          operands[2]));
+    DONE;
+  }
+)
+
 ;; Lane extraction of a value, neither sign nor zero extension
 ;; is guaranteed so upper bits should be considered undefined.
 (define_insn "aarch64_get_lane<mode>"

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index ac87d7065d126d5fca933d34ead4bc876e620908..1dcff675f03fd84f8888186cb1f059f900e740c1 100644 (file)
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -457,7 +457,7 @@ typedef struct poly16x8x4_t
 
 #define __aarch64_vget_lane_any(__size, __cast_ret, __cast_a, __a, __b) \
   (__cast_ret                                                          \
-     __builtin_aarch64_get_lane##__size (__cast_a __a, __b))
+     __builtin_aarch64_be_checked_get_lane##__size (__cast_a __a, __b))
 
 #define __aarch64_vget_lane_f32(__a, __b) \
   __aarch64_vget_lane_any (v2sf, , , __a, __b)