Accidentally commented out tests

diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index b6e10585442d1201124d77d8ddb3ff779c5deca7..4b7716739b4c2ef52bee1a392a808a5baa48e744 100644 (file)
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -1,52 +1,52 @@
 ### TODO: Not running equivalence checking because BRAM models does not exists
 ###       currently. Checking instance counts instead.
-## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
-#read_verilog ../common/blockram.v
-#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
-#synth_xilinx -top sync_ram_sdp
-#cd sync_ram_sdp
-#select -assert-count 1 t:RAMB18E1
-#
-#design -reset
-#read_verilog ../common/blockram.v
-#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
-#synth_xilinx -top sync_ram_sdp
-#cd sync_ram_sdp
-#select -assert-count 1 t:RAMB18E1
-#
-#design -reset
-#read_verilog ../common/blockram.v
-#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
-#synth_xilinx -top sync_ram_sdp
-#cd sync_ram_sdp
-#select -assert-count 1 t:RAMB18E1
-#
-#design -reset
-#read_verilog ../common/blockram.v
-#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
-#synth_xilinx -top sync_ram_sdp
-#cd sync_ram_sdp
-#select -assert-count 1 t:RAMB18E1
-#
-## Anything memory bits < 1024 -> LUTRAM
-#design -reset
-#read_verilog ../common/blockram.v
-#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
-#synth_xilinx -top sync_ram_sdp
-#cd sync_ram_sdp
-#select -assert-count 0 t:RAMB18E1
-#select -assert-count 4 t:RAM128X1D
-#
-## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 
-#design -reset
-#read_verilog ../common/blockram.v
-#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
-#synth_xilinx -top sync_ram_sdp
-#cd sync_ram_sdp
-#select -assert-count 1 t:RAMB36E1
-#
-#
-#### With parameters
+# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+# Anything memory bits < 1024 -> LUTRAM
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 0 t:RAMB18E1
+select -assert-count 4 t:RAM128X1D
+
+# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB36E1
+
+
+### With parameters
 
 design -reset
 read_verilog ../common/blockram.v