(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 642e9e8d1c21cea632e3c0a4b54916fbc60530f3..ae8a0616f7c86fce13016eaefc19399d9c733d2c 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -985,10 +985,14 @@ literally, and assume always a little-endian layout:
 
     elreg_t int_regfile[128];
 
-    get_polymorphed_reg(reg, bitwidth, offset):
-        el_reg_t res;
+Accessing (get and set) of registers given a value, register (in `elreg_t`
+form), and that all arithmetic, numbering and pseudo-Memory format is
+LE-endian and LSB0-numbered below:
+
+    elreg_t& get_polymorphed_reg(elreg_t const& reg, bitwidth, offset):
+        el_reg_t res; // result
         res.l = 0; // TODO: going to need sign-extending / zero-extending
-        if !reg.isvec: // scalar has no element offset
+        if !reg.isvec: // scalar access has no element offset
             offset = 0
         if bitwidth == 8:
             reg.b = int_regfile[reg].b[offset]
@@ -998,9 +1002,9 @@ literally, and assume always a little-endian layout:
             reg.i = int_regfile[reg].i[offset]
         elif bitwidth == 64:
             reg.l = int_regfile[reg].l[offset]
-        return res & bytemask
+        return reg
 
-    set_polymorphed_reg(reg, bitwidth, offset, val):
+    set_polymorphed_reg(elreg_t& reg, bitwidth, offset, val):
         if (!reg.isvec):
             # for safety mask out hi bits
             bytemask = (8 << bitwidth) - 1