#define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
-static INLINE void update_reloc_domains(struct drm_radeon_cs_reloc *reloc,
- enum radeon_bo_domain rd,
- enum radeon_bo_domain wd,
- enum radeon_bo_domain *added_domains)
+static INLINE void update_reloc(struct drm_radeon_cs_reloc *reloc,
+ enum radeon_bo_domain rd,
+ enum radeon_bo_domain wd,
+ unsigned priority,
+ enum radeon_bo_domain *added_domains)
{
*added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
reloc->read_domains |= rd;
reloc->write_domain |= wd;
+ reloc->flags = MAX2(reloc->flags, priority);
}
int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
struct radeon_bo *bo,
enum radeon_bo_usage usage,
enum radeon_bo_domain domains,
+ unsigned priority,
enum radeon_bo_domain *added_domains)
{
struct radeon_cs_context *csc = cs->csc;
bool update_hash = TRUE;
int i;
+ priority = MIN2(priority, 15);
*added_domains = 0;
+
if (csc->is_handle_added[hash]) {
i = csc->reloc_indices_hashlist[hash];
reloc = &csc->relocs[i];
* update the cmd stream with proper buffer offset).
*/
update_hash = FALSE;
- update_reloc_domains(reloc, rd, wd, added_domains);
+ update_reloc(reloc, rd, wd, priority, added_domains);
if (cs->base.ring_type != RING_DMA) {
csc->reloc_indices_hashlist[hash] = i;
return i;
reloc->handle = bo->handle;
reloc->read_domains = rd;
reloc->write_domain = wd;
- reloc->flags = 0;
+ reloc->flags = priority;
csc->is_handle_added[hash] = TRUE;
if (update_hash) {
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_bo *bo = (struct radeon_bo*)buf;
enum radeon_bo_domain added_domains;
- unsigned index = radeon_add_reloc(cs, bo, usage, domains, &added_domains);
+ unsigned index = radeon_add_reloc(cs, bo, usage, domains, 0, &added_domains);
if (added_domains & RADEON_DOMAIN_GTT)
cs->csc->used_gart += bo->base.size;
RADEON_TIMESTAMP
};
+enum radeon_bo_priority {
+ RADEON_PRIO_MIN,
+ RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
+ RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
+ RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
+ RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
+ RADEON_PRIO_COLOR_BUFFER,
+ RADEON_PRIO_DEPTH_BUFFER,
+ RADEON_PRIO_SHADER_TEXTURE_MSAA,
+ RADEON_PRIO_COLOR_BUFFER_MSAA,
+ RADEON_PRIO_DEPTH_BUFFER_MSAA,
+ RADEON_PRIO_COLOR_META,
+ RADEON_PRIO_DEPTH_META,
+ RADEON_PRIO_MAX /* must be <= 15 */
+};
+
struct winsys_handle;
struct radeon_winsys_cs_handle;
* \param buf A winsys buffer to validate.
* \param usage Whether the buffer is used for read and/or write.
* \param domain Bitmask of the RADEON_DOMAIN_* flags.
+ * \param priority A higher number means a greater chance of being
+ * placed in the requested domain. 15 is the maximum.
* \return Relocation index.
*/
unsigned (*cs_add_reloc)(struct radeon_winsys_cs *cs,
struct radeon_winsys_cs_handle *buf,
enum radeon_bo_usage usage,
- enum radeon_bo_domain domain);
+ enum radeon_bo_domain domain/*,
+ enum radeon_bo_priority priority*/);
/**
* Return TRUE if there is enough memory in VRAM and GTT for the relocs