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diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
index c4343bde5cfb68877902b96c05fc80d0f5eda752..77a23c33c2e95bb10ef8dec3ddca09bc237c42bd 100644 (file)
--- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn
+++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
@@ -6,9 +6,9 @@
 
 RVP implementations may choose to load/store to/from Integer register file (rather than from a dedicated Vector register file).
 
-* VLD and VST in this case will have similar behaviour to LW/LD and SW/SD respectively, but only operate on up to VL elements (see point #4 below).   
-* Mapping of v0-31 <-> r0-31 **is fixed** at 1:1.  (An exception may be made to map v1 to r5, as otherwise may clash with procedure linkage).
 * Thus, RVP implementations have a choice of providing a dedicated Vector register file, or sharing the integer register file, but not both  simultaneously.  (Supporting both would need a CSR mode switch bit).
+* Mapping of v0-31 <-> r0-31 **is fixed** at 1:1.  (An exception may be made to map v1 to r5, as otherwise may clash with procedure linkage).
+* VLD and VST in this case will have similar behaviour to LW/LD and SW/SD respectively, but only operate on up to VL elements (see point #4 below).   
 * If integer register file is used for vector operations, any callee saved registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions, before being used as vector registers (this register saving behaviour is harmless but redundant when RVP code is run on a machine with a dedicated vector reg file).
 
 ##### VLDX, VSTX, VLDS, VSTS are not supported in hardware