projects
/
riscv-isa-sim.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
60535c2
)
fix cache line index offset in cachesim.cc
author
Wei Song
<wsong83@gmail.com>
Mon, 13 Apr 2015 15:35:13 +0000
(16:35 +0100)
committer
Wei Song
<wsong83@gmail.com>
Mon, 13 Apr 2015 15:35:13 +0000
(16:35 +0100)
riscv/cachesim.cc
patch
|
blob
|
history
diff --git
a/riscv/cachesim.cc
b/riscv/cachesim.cc
index 9a1118708987fadc18abfbc627cb4d9f46d730e1..90ab5be3d9ff168db3cbc769e3ac550d6b2b41ea 100644
(file)
--- a/
riscv/cachesim.cc
+++ b/
riscv/cachesim.cc
@@
-45,7
+45,7
@@
void cache_sim_t::init()
help();
idx_shift = 0;
- for (size_t x = linesz; x; x >>= 1)
+ for (size_t x = linesz; x
>1
; x >>= 1)
idx_shift++;
tags = new uint64_t[sets*ways]();