re PR target/55426 (gcc.target/arm/neon-vld1_dupQ.c ICEs on armeb)

	PR target/55426
	* config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit
	conversions.

From-SVN: r208116

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0f3d80c6c3c420548a6460ef1214b30e6aa8dfe9..4042cf9f31c68472e2015a76bea49fb89fe4eae5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-02-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/55426
+       * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit
+       conversions.
+
 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 
        * common/config/i386/i386-common.c (OPTION_MASK_ISA_PREFETCHWT1_SET),

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index d9d3547458e96e02663ab0acc6759f5a788e7b65..7ca47a7ec70faeef510a05b7f5d388ed06f53301 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1257,11 +1257,15 @@ enum reg_class
    VFPv2.
    In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
    VFP registers in little-endian order.  We can't describe that accurately to
-   GCC, so avoid taking subregs of such values.  */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)      \
-  (TARGET_VFP && TARGET_BIG_END                                \
-   && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD           \
-       || GET_MODE_SIZE (TO) > UNITS_PER_WORD)         \
+   GCC, so avoid taking subregs of such values.
+   The only exception is going from a 128-bit to a 64-bit type.  In that case
+   the data layout happens to be consistent for big-endian, so we explicitly allow
+   that case.  */
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)              \
+  (TARGET_VFP && TARGET_BIG_END                                        \
+   && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
+   && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD                   \
+       || GET_MODE_SIZE (TO) > UNITS_PER_WORD)                 \
    && reg_classes_intersect_p (VFP_REGS, (CLASS)))
 
 /* The class value for index registers, and the one for base regs.  */