Use XDR for address pins

diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py
index 0f8cd411854b89c042f2ae7ece8304c11d8ab679..baa9c7cb6f69a5440b14cd4fa087f6ed545b4e1d 100644 (file)
--- a/examples/headless-ecpix5.py
+++ b/examples/headless-ecpix5.py
@@ -33,7 +33,7 @@ class DDR3SoC(SoC, Elaboratable):
         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
 
         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
-            xdr={"clk":4})
+            xdr={"clk":4, "a":4})
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 97d1d7eedd9d9168f24a120a61adffc5e467e840..ec554ccf6de704c79a1c8124202eeb78254922fa 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -104,7 +104,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
         self.bus = self._bridge.bus
 
-        addressbits = len(self.pads.a.o)
+        addressbits = len(self.pads.a.o0)
         bankbits = len(self.pads.ba.o)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o)
         databits = len(self.pads.dq.io)
@@ -115,8 +115,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         nphases = 2
         databits = len(self.pads.dq.io)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o)
-        addressbits = len(self.pads.a.o)
-        bankbits = len(self.pads.ba.o)
         cl, cwl = get_cl_cw("DDR3", tck)
         cl_sys_latency = get_sys_latency(nphases, cl)
         cwl_sys_latency = get_sys_latency(nphases, cwl)
@@ -148,7 +146,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         nphases = 2
         databits = len(self.pads.dq.io)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o)
-        addressbits = len(self.pads.a.o)
+        addressbits = len(self.pads.a.o0)
         bankbits = len(self.pads.ba.o)
 
         # Init -------------------------------------------------------------------------------------
@@ -182,17 +180,17 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             ]
 
         # Addresses and Commands ---------------------------------------------------------------
+        m.d.comb += [
+            self.pads.a.o_clk.eq(ClockSignal("dramsync")),
+            self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
+        ]
         for i in range(addressbits):
-            m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("dramsync"),
-                                     i_ECLK=ClockSignal("sync2x"),
-                                     i_SCLK=ClockSignal(),
-                                     i_D0=dfi.phases[0].address[i],
-                                     i_D1=dfi.phases[0].address[i],
-                                     i_D2=dfi.phases[1].address[i],
-                                     i_D3=dfi.phases[1].address[i],
-                                     o_Q=self.pads.a.o[i]
-                                     )
+            m.d.comb += [
+                self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
+                self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
+                self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
+                self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
+            ]
         for i in range(bankbits):
             m.submodules += Instance("ODDRX2F",
                                      i_RST=ResetSignal("dramsync"),

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index d932d8bd7c1ef35d1ef46f3d628f2a833abb8808..5822e0544df2c035ec354057a5db6abf800606b1 100644 (file)
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -30,7 +30,7 @@ class DDR3SoC(SoC, Elaboratable):
         self._arbiter.add(self.ub.bus)
 
         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
-            xdr={"clk":4})
+            xdr={"clk":4, "a":4})
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)