anv: implement WaEnableStateCacheRedirectToCS
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Thu, 18 Apr 2019 11:00:19 +0000 (12:00 +0100)
committerLionel Landwerlin <lionel.g.landwerlin@intel.com>
Thu, 18 Apr 2019 16:43:08 +0000 (17:43 +0100)
This 3d performance workaround was initially put in the kernel but the
media driver requires different settings so the register has been
whitelisted in i915 [1] and userspace drivers are left initializing it as
they wish.

[1] : https://patchwork.freedesktop.org/series/59494/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
src/intel/vulkan/genX_state.c

index 6d55e5dc5c6f7badafdcb628a4a537f998d6170c..283cd8c501a7e23a12355fa8bbfbbe4281ecd57b 100644 (file)
@@ -212,6 +212,17 @@ genX(init_device_state)(struct anv_device *device)
       lri.DataDWord      = common_slice_chicken3;
    }
 
+   /* WaEnableStateCacheRedirectToCS:icl */
+   uint32_t slice_common_eco_chicken1;
+   anv_pack_struct(&slice_common_eco_chicken1,
+                   GENX(SLICE_COMMON_ECO_CHICKEN1),
+                   .StateCacheRedirectToCSSectionEnable = true,
+                   .StateCacheRedirectToCSSectionEnableMask = true);
+
+   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+      lri.RegisterOffset = GENX(SLICE_COMMON_ECO_CHICKEN1_num);
+      lri.DataDWord      = slice_common_eco_chicken1;
+   }
 #endif
 
    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so