ice40_dsp: fix typo

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 202a43f0c6729e8ba56f846224b23a68f8761980..c364cd91aefefbd099252018d4edf1caf2f0e73b 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
        // SB_MAC16 Input Interface
        SigSpec A = st.sigA;
-       A.extend_u0(16, st.mul->connections_.at(ID(A_SIGNED), State::S0).as_bool());
+       A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
        log_assert(GetSize(A) == 16);
 
        SigSpec B = st.sigB;
-       B.extend_u0(16, st.mul->connections_.at(ID(B_SIGNED), State::S0).as_bool());
+       B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
        log_assert(GetSize(B) == 16);
 
        SigSpec CD = st.sigCD;

diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys
new file mode 100644 (file)
index 0000000..3b9f529
--- /dev/null
+++ b/tests/arch/xilinx/xilinx_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
+DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
+assign o2 = a * 16'd0;
+wire [42:0] o3, o4;
+DSP48E1 m2 (.A(a), .B(b), .P(o3));
+assign o4 = a * b;
+DSP48E1 m3 (.A(a), .B(b), .P(o5));
+endmodule
+EOT
+xilinx_dsp