i965: Enable ARB_gpu_shader_int64 on Gen8+

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index 4159756fc5da24acb04c2e34152c50cf88c14d44..977feb37fc2f5768cbf3246ea5678b5cfb856b5a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -120,6 +120,11 @@ process_glsl_ir(struct brw_context *brw,
    }
 
    lower_instructions(shader->ir, instructions_to_lower);
+   lower_64bit_integer_instructions(shader->ir,
+                                    MUL64 |
+                                    DIV64 |
+                                    MOD64 |
+                                    SIGN64);
 
    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
     * if-statements need to be flattened.

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index b674b2f494cfb9070d9dafceca45bb47891d62c9..f1290bf7b4943fec9009830362e0314a8c8d637d 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -264,6 +264,7 @@ intelInitExtensions(struct gl_context *ctx)
    }
 
    if (brw->gen >= 8) {
+      ctx->Extensions.ARB_gpu_shader_int64 = true;
       ctx->Extensions.ARB_ES3_2_compatibility = true;
    }