soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 03b7e426c0e2622428d263a90b426fabb5a33618..252cd491631933c75d639d70e1cb2717f6cf51ee 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -448,7 +448,7 @@ class iCE40PLL(Module):
                         valid = False
                         for divq in range(*self.divq_range):
                             clk_freq = vco_freq/(2**divq)
-                            if abs(clk_freq - f) < f*m:
+                            if abs(clk_freq - f) <= f*m:
                                 config["divq"] = divq
                                 valid = True
                                 break
@@ -541,7 +541,7 @@ class ECP5PLL(Module):
                     valid = False
                     for d in range(*self.clko_div_range):
                         clk_freq = vco_freq/d
-                        if abs(clk_freq - f) < f*m:
+                        if abs(clk_freq - f) <= f*m:
                             config["clko{}_freq".format(n)] = clk_freq
                             config["clko{}_div".format(n)] = d
                             config["clko{}_phase".format(n)] = p