(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index cfbe04b1ed2e5fcc2eb012a3a414c2d56f1beef6..c85d349d311b761b22a938a059f31f7a2bf3a589 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -232,3 +232,21 @@ element result is *always* discarded, never written (just like `cmp`).
 Note that predication is still respected: predicate zeroing is slightly
 different: elements that fail the CR test *or* are masked out are zero'd.
 
+# Pack/Unpack Mode
+
+Structured Pack/Unpack is similar to VSX `vpack` and `vunpack` except
+generalised not only to a Schedule to be applied to any operation but
+also extended to vec2/3/4.
+
+Setting this mode changes the meaning of bits 4-5 in `RM` from being
+`ELWIDTH` to a pair of Pack/Unpack bits.  Thus it is not possible
+to separately override source and destination elwidths at the same
+time as use Pack/Unpack: the `SRC_ELWIDTH` bits (6-7) must be used as
+both source and destination elwidth.
+
+This was considered to be an acceptable
+compromise.  If separate elwidths are required and Pack/Unpack
+needed without needing to perform a widening or narrowing register
+move then [[sv/remap]] may be used: Matrix Mode may perform the
+same operation (but is more costly to set up).
+