all.texi
as.1
as.texinfo
+c-a29k.texi
+c-h8300.texi
+c-h8500.texi
+c-hppa.texi
+c-i386.texi
+c-i960.texi
+c-m68k.texi
+c-mips.texi
+c-sh.texi
+c-sparc.texi
+c-vax.texi
+c-z8k.texi
gasp.texi
h8.texi
internals.texi
--- /dev/null
+@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node AMD29K-Dependent
+@chapter AMD 29K Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter AMD 29K Dependent Features
+@end ifclear
+
+@cindex AMD 29K support
+@cindex 29K support
+@menu
+* AMD29K Options:: Options
+* AMD29K Syntax:: Syntax
+* AMD29K Floating Point:: Floating Point
+* AMD29K Directives:: AMD 29K Machine Directives
+* AMD29K Opcodes:: Opcodes
+@end menu
+
+@node AMD29K Options
+@section Options
+@cindex AMD 29K options (none)
+@cindex options for AMD29K (none)
+@code{@value{AS}} has no additional command-line options for the AMD
+29K family.
+
+@node AMD29K Syntax
+@section Syntax
+@menu
+* AMD29K-Chars:: Special Characters
+* AMD29K-Regs:: Register Names
+@end menu
+
+@node AMD29K-Chars
+@subsection Special Characters
+
+@cindex line comment character, AMD 29K
+@cindex AMD 29K line comment character
+@samp{;} is the line comment character.
+
+@cindex line separator, AMD 29K
+@cindex AMD 29K line separator
+@cindex statement separator, AMD 29K
+@cindex AMD 29K statement separator
+@samp{@@} can be used instead of a newline to separate statements.
+
+@cindex identifiers, AMD 29K
+@cindex AMD 29K identifiers
+The character @samp{?} is permitted in identifiers (but may not begin
+an identifier).
+
+@node AMD29K-Regs
+@subsection Register Names
+
+@cindex AMD 29K register names
+@cindex register names, AMD 29K
+General-purpose registers are represented by predefined symbols of the
+form @samp{GR@var{nnn}} (for global registers) or @samp{LR@var{nnn}}
+(for local registers), where @var{nnn} represents a number between
+@code{0} and @code{127}, written with no leading zeros. The leading
+letters may be in either upper or lower case; for example, @samp{gr13}
+and @samp{LR7} are both valid register names.
+
+You may also refer to general-purpose registers by specifying the
+register number as the result of an expression (prefixed with @samp{%%}
+to flag the expression as a register number):
+@smallexample
+%%@var{expression}
+@end smallexample
+@noindent
+---where @var{expression} must be an absolute expression evaluating to a
+number between @code{0} and @code{255}. The range [0, 127] refers to
+global registers, and the range [128, 255] to local registers.
+
+@cindex special purpose registers, AMD 29K
+@cindex AMD 29K special purpose registers
+@cindex protected registers, AMD 29K
+@cindex AMD 29K protected registers
+In addition, @code{@value{AS}} understands the following protected
+special-purpose register names for the AMD 29K family:
+
+@smallexample
+ vab chd pc0
+ ops chc pc1
+ cps rbp pc2
+ cfg tmc mmu
+ cha tmr lru
+@end smallexample
+
+These unprotected special-purpose register names are also recognized:
+@smallexample
+ ipc alu fpe
+ ipa bp inte
+ ipb fc fps
+ q cr exop
+@end smallexample
+
+@node AMD29K Floating Point
+@section Floating Point
+
+@cindex floating point, AMD 29K (@sc{ieee})
+@cindex AMD 29K floating point (@sc{ieee})
+The AMD 29K family uses @sc{ieee} floating-point numbers.
+
+@node AMD29K Directives
+@section AMD 29K Machine Directives
+
+@cindex machine directives, AMD 29K
+@cindex AMD 29K machine directives
+@table @code
+@item .block @var{size} , @var{fill}
+@cindex @code{block} directive, AMD 29K
+This directive emits @var{size} bytes, each of value @var{fill}. Both
+@var{size} and @var{fill} are absolute expressions. If the comma
+and @var{fill} are omitted, @var{fill} is assumed to be zero.
+
+In other versions of the @sc{gnu} assembler, this directive is called
+@samp{.space}.
+@end table
+
+@table @code
+@item .cputype
+@cindex @code{cputype} directive, AMD 29K
+This directive is ignored; it is accepted for compatibility with other
+AMD 29K assemblers.
+
+@item .file
+@cindex @code{file} directive, AMD 29K
+This directive is ignored; it is accepted for compatibility with other
+AMD 29K assemblers.
+
+@quotation
+@emph{Warning:} in other versions of the @sc{gnu} assembler, @code{.file} is
+used for the directive called @code{.app-file} in the AMD 29K support.
+@end quotation
+
+@item .line
+@cindex @code{line} directive, AMD 29K
+This directive is ignored; it is accepted for compatibility with other
+AMD 29K assemblers.
+
+@ignore
+@c since we're ignoring .lsym...
+@item .reg @var{symbol}, @var{expression}
+@cindex @code{reg} directive, AMD 29K
+@code{.reg} has the same effect as @code{.lsym}; @pxref{Lsym,,@code{.lsym}}.
+@end ignore
+
+@item .sect
+@cindex @code{sect} directive, AMD 29K
+This directive is ignored; it is accepted for compatibility with other
+AMD 29K assemblers.
+
+@item .use @var{section name}
+@cindex @code{use} directive, AMD 29K
+Establishes the section and subsection for the following code;
+@var{section name} may be one of @code{.text}, @code{.data},
+@code{.data1}, or @code{.lit}. With one of the first three @var{section
+name} options, @samp{.use} is equivalent to the machine directive
+@var{section name}; the remaining case, @samp{.use .lit}, is the same as
+@samp{.data 200}.
+@end table
+
+@node AMD29K Opcodes
+@section Opcodes
+
+@cindex AMD 29K opcodes
+@cindex opcodes for AMD 29K
+@code{@value{AS}} implements all the standard AMD 29K opcodes. No
+additional pseudo-instructions are needed on this family.
+
+For information on the 29K machine instruction set, see @cite{Am29000
+User's Manual}, Advanced Micro Devices, Inc.
+
--- /dev/null
+@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@end ifset
+@node H8/300-Dependent
+@chapter H8/300 Dependent Features
+
+@cindex H8/300 support
+@menu
+* H8/300 Options:: Options
+* H8/300 Syntax:: Syntax
+* H8/300 Floating Point:: Floating Point
+* H8/300 Directives:: H8/300 Machine Directives
+* H8/300 Opcodes:: Opcodes
+@end menu
+
+@node H8/300 Options
+@section Options
+
+@cindex H8/300 options (none)
+@cindex options, H8/300 (none)
+@code{@value{AS}} has no additional command-line options for the Hitachi
+H8/300 family.
+
+@node H8/300 Syntax
+@section Syntax
+@menu
+* H8/300-Chars:: Special Characters
+* H8/300-Regs:: Register Names
+* H8/300-Addressing:: Addressing Modes
+@end menu
+
+@node H8/300-Chars
+@subsection Special Characters
+
+@cindex line comment character, H8/300
+@cindex H8/300 line comment character
+@samp{;} is the line comment character.
+
+@cindex line separator, H8/300
+@cindex statement separator, H8/300
+@cindex H8/300 line separator
+@samp{$} can be used instead of a newline to separate statements.
+Therefore @emph{you may not use @samp{$} in symbol names} on the H8/300.
+
+@node H8/300-Regs
+@subsection Register Names
+
+@cindex H8/300 registers
+@cindex register names, H8/300
+You can use predefined symbols of the form @samp{r@var{n}h} and
+@samp{r@var{n}l} to refer to the H8/300 registers as sixteen 8-bit
+general-purpose registers. @var{n} is a digit from @samp{0} to
+@samp{7}); for instance, both @samp{r0h} and @samp{r7l} are valid
+register names.
+
+You can also use the eight predefined symbols @samp{r@var{n}} to refer
+to the H8/300 registers as 16-bit registers (you must use this form for
+addressing).
+
+On the H8/300H, you can also use the eight predefined symbols
+@samp{er@var{n}} (@samp{er0} @dots{} @samp{er7}) to refer to the 32-bit
+general purpose registers.
+
+The two control registers are called @code{pc} (program counter; a
+16-bit register, except on the H8/300H where it is 24 bits) and
+@code{ccr} (condition code register; an 8-bit register). @code{r7} is
+used as the stack pointer, and can also be called @code{sp}.
+
+@node H8/300-Addressing
+@subsection Addressing Modes
+
+@cindex addressing modes, H8/300
+@cindex H8/300 addressing modes
+@value{AS} understands the following addressing modes for the H8/300:
+@table @code
+@item r@var{n}
+Register direct
+
+@item @@r@var{n}
+Register indirect
+
+@item @@(@var{d}, r@var{n})
+@itemx @@(@var{d}:16, r@var{n})
+@itemx @@(@var{d}:24, r@var{n})
+Register indirect: 16-bit or 24-bit displacement @var{d} from register
+@var{n}. (24-bit displacements are only meaningful on the H8/300H.)
+
+@item @@r@var{n}+
+Register indirect with post-increment
+
+@item @@-r@var{n}
+Register indirect with pre-decrement
+
+@item @code{@@}@var{aa}
+@itemx @code{@@}@var{aa}:8
+@itemx @code{@@}@var{aa}:16
+@itemx @code{@@}@var{aa}:24
+Absolute address @code{aa}. (The address size @samp{:24} only makes
+sense on the H8/300H.)
+
+@item #@var{xx}
+@itemx #@var{xx}:8
+@itemx #@var{xx}:16
+@itemx #@var{xx}:32
+Immediate data @var{xx}. You may specify the @samp{:8}, @samp{:16}, or
+@samp{:32} for clarity, if you wish; but @code{@value{AS}} neither
+requires this nor uses it---the data size required is taken from
+context.
+
+@item @code{@@}@code{@@}@var{aa}
+@itemx @code{@@}@code{@@}@var{aa}:8
+Memory indirect. You may specify the @samp{:8} for clarity, if you
+wish; but @code{@value{AS}} neither requires this nor uses it.
+@end table
+
+@node H8/300 Floating Point
+@section Floating Point
+
+@cindex floating point, H8/300 (@sc{ieee})
+@cindex H8/300 floating point (@sc{ieee})
+The H8/300 family has no hardware floating point, but the @code{.float}
+directive generates @sc{ieee} floating-point numbers for compatibility
+with other development tools.
+
+@page
+@node H8/300 Directives
+@section H8/300 Machine Directives
+
+@cindex H8/300 machine directives (none)
+@cindex machine directives, H8/300 (none)
+@cindex @code{word} directive, H8/300
+@cindex @code{int} directive, H8/300
+@code{@value{AS}} has only one machine-dependent directive for the
+H8/300:
+
+@table @code
+@cindex H8/300H, assembling for
+@item .h8300h
+Recognize and emit additional instructions for the H8/300H variant, and
+also make @code{.int} emit 32-bit numbers rather than the usual (16-bit)
+for the H8/300 family.
+@end table
+
+On the H8/300 family (including the H8/300H) @samp{.word} directives
+generate 16-bit numbers.
+
+@node H8/300 Opcodes
+@section Opcodes
+
+@cindex H8/300 opcode summary
+@cindex opcode summary, H8/300
+@cindex mnemonics, H8/300
+@cindex instruction summary, H8/300
+For detailed information on the H8/300 machine instruction set, see
+@cite{H8/300 Series Programming Manual} (Hitachi ADE--602--025). For
+information specific to the H8/300H, see @cite{H8/300H Series
+Programming Manual} (Hitachi).
+
+@code{@value{AS}} implements all the standard H8/300 opcodes. No additional
+pseudo-instructions are needed on this family.
+
+@ifset SMALL
+@c this table, due to the multi-col faking and hardcoded order, looks silly
+@c except in smallbook. See comments below "@set SMALL" near top of this file.
+
+The following table summarizes the H8/300 opcodes, and their arguments.
+Entries marked @samp{*} are opcodes used only on the H8/300H.
+
+@smallexample
+@c Using @group seems to use the normal baselineskip, not the smallexample
+@c baselineskip; looks approx doublespaced.
+ @i{Legend:}
+ Rs @r{source register}
+ Rd @r{destination register}
+ abs @r{absolute address}
+ imm @r{immediate data}
+ disp:N @r{N-bit displacement from a register}
+ pcrel:N @r{N-bit displacement relative to program counter}
+
+ add.b #imm,rd * andc #imm,ccr
+ add.b rs,rd band #imm,rd
+ add.w rs,rd band #imm,@@rd
+* add.w #imm,rd band #imm,@@abs:8
+* add.l rs,rd bra pcrel:8
+* add.l #imm,rd * bra pcrel:16
+ adds #imm,rd bt pcrel:8
+ addx #imm,rd * bt pcrel:16
+ addx rs,rd brn pcrel:8
+ and.b #imm,rd * brn pcrel:16
+ and.b rs,rd bf pcrel:8
+* and.w rs,rd * bf pcrel:16
+* and.w #imm,rd bhi pcrel:8
+* and.l #imm,rd * bhi pcrel:16
+* and.l rs,rd bls pcrel:8
+@page
+* bls pcrel:16 bld #imm,rd
+ bcc pcrel:8 bld #imm,@@rd
+* bcc pcrel:16 bld #imm,@@abs:8
+ bhs pcrel:8 bnot #imm,rd
+* bhs pcrel:16 bnot #imm,@@rd
+ bcs pcrel:8 bnot #imm,@@abs:8
+* bcs pcrel:16 bnot rs,rd
+ blo pcrel:8 bnot rs,@@rd
+* blo pcrel:16 bnot rs,@@abs:8
+ bne pcrel:8 bor #imm,rd
+* bne pcrel:16 bor #imm,@@rd
+ beq pcrel:8 bor #imm,@@abs:8
+* beq pcrel:16 bset #imm,rd
+ bvc pcrel:8 bset #imm,@@rd
+* bvc pcrel:16 bset #imm,@@abs:8
+ bvs pcrel:8 bset rs,rd
+* bvs pcrel:16 bset rs,@@rd
+ bpl pcrel:8 bset rs,@@abs:8
+* bpl pcrel:16 bsr pcrel:8
+ bmi pcrel:8 bsr pcrel:16
+* bmi pcrel:16 bst #imm,rd
+ bge pcrel:8 bst #imm,@@rd
+* bge pcrel:16 bst #imm,@@abs:8
+ blt pcrel:8 btst #imm,rd
+* blt pcrel:16 btst #imm,@@rd
+ bgt pcrel:8 btst #imm,@@abs:8
+* bgt pcrel:16 btst rs,rd
+ ble pcrel:8 btst rs,@@rd
+* ble pcrel:16 btst rs,@@abs:8
+ bclr #imm,rd bxor #imm,rd
+ bclr #imm,@@rd bxor #imm,@@rd
+ bclr #imm,@@abs:8 bxor #imm,@@abs:8
+ bclr rs,rd cmp.b #imm,rd
+ bclr rs,@@rd cmp.b rs,rd
+ bclr rs,@@abs:8 cmp.w rs,rd
+ biand #imm,rd cmp.w rs,rd
+ biand #imm,@@rd * cmp.w #imm,rd
+ biand #imm,@@abs:8 * cmp.l #imm,rd
+ bild #imm,rd * cmp.l rs,rd
+ bild #imm,@@rd daa rs
+ bild #imm,@@abs:8 das rs
+ bior #imm,rd dec.b rs
+ bior #imm,@@rd * dec.w #imm,rd
+ bior #imm,@@abs:8 * dec.l #imm,rd
+ bist #imm,rd divxu.b rs,rd
+ bist #imm,@@rd * divxu.w rs,rd
+ bist #imm,@@abs:8 * divxs.b rs,rd
+ bixor #imm,rd * divxs.w rs,rd
+ bixor #imm,@@rd eepmov
+ bixor #imm,@@abs:8 * eepmovw
+@page
+* exts.w rd mov.w rs,@@abs:16
+* exts.l rd * mov.l #imm,rd
+* extu.w rd * mov.l rs,rd
+* extu.l rd * mov.l @@rs,rd
+ inc rs * mov.l @@(disp:16,rs),rd
+* inc.w #imm,rd * mov.l @@(disp:24,rs),rd
+* inc.l #imm,rd * mov.l @@rs+,rd
+ jmp @@rs * mov.l @@abs:16,rd
+ jmp abs * mov.l @@abs:24,rd
+ jmp @@@@abs:8 * mov.l rs,@@rd
+ jsr @@rs * mov.l rs,@@(disp:16,rd)
+ jsr abs * mov.l rs,@@(disp:24,rd)
+ jsr @@@@abs:8 * mov.l rs,@@-rd
+ ldc #imm,ccr * mov.l rs,@@abs:16
+ ldc rs,ccr * mov.l rs,@@abs:24
+* ldc @@abs:16,ccr movfpe @@abs:16,rd
+* ldc @@abs:24,ccr movtpe rs,@@abs:16
+* ldc @@(disp:16,rs),ccr mulxu.b rs,rd
+* ldc @@(disp:24,rs),ccr * mulxu.w rs,rd
+* ldc @@rs+,ccr * mulxs.b rs,rd
+* ldc @@rs,ccr * mulxs.w rs,rd
+* mov.b @@(disp:24,rs),rd neg.b rs
+* mov.b rs,@@(disp:24,rd) * neg.w rs
+ mov.b @@abs:16,rd * neg.l rs
+ mov.b rs,rd nop
+ mov.b @@abs:8,rd not.b rs
+ mov.b rs,@@abs:8 * not.w rs
+ mov.b rs,rd * not.l rs
+ mov.b #imm,rd or.b #imm,rd
+ mov.b @@rs,rd or.b rs,rd
+ mov.b @@(disp:16,rs),rd * or.w #imm,rd
+ mov.b @@rs+,rd * or.w rs,rd
+ mov.b @@abs:8,rd * or.l #imm,rd
+ mov.b rs,@@rd * or.l rs,rd
+ mov.b rs,@@(disp:16,rd) orc #imm,ccr
+ mov.b rs,@@-rd pop.w rs
+ mov.b rs,@@abs:8 * pop.l rs
+ mov.w rs,@@rd push.w rs
+* mov.w @@(disp:24,rs),rd * push.l rs
+* mov.w rs,@@(disp:24,rd) rotl.b rs
+* mov.w @@abs:24,rd * rotl.w rs
+* mov.w rs,@@abs:24 * rotl.l rs
+ mov.w rs,rd rotr.b rs
+ mov.w #imm,rd * rotr.w rs
+ mov.w @@rs,rd * rotr.l rs
+ mov.w @@(disp:16,rs),rd rotxl.b rs
+ mov.w @@rs+,rd * rotxl.w rs
+ mov.w @@abs:16,rd * rotxl.l rs
+ mov.w rs,@@(disp:16,rd) rotxr.b rs
+ mov.w rs,@@-rd * rotxr.w rs
+@page
+* rotxr.l rs * stc ccr,@@(disp:24,rd)
+ bpt * stc ccr,@@-rd
+ rte * stc ccr,@@abs:16
+ rts * stc ccr,@@abs:24
+ shal.b rs sub.b rs,rd
+* shal.w rs sub.w rs,rd
+* shal.l rs * sub.w #imm,rd
+ shar.b rs * sub.l rs,rd
+* shar.w rs * sub.l #imm,rd
+* shar.l rs subs #imm,rd
+ shll.b rs subx #imm,rd
+* shll.w rs subx rs,rd
+* shll.l rs * trapa #imm
+ shlr.b rs xor #imm,rd
+* shlr.w rs xor rs,rd
+* shlr.l rs * xor.w #imm,rd
+ sleep * xor.w rs,rd
+ stc ccr,rd * xor.l #imm,rd
+* stc ccr,@@rs * xor.l rs,rd
+* stc ccr,@@(disp:16,rd) xorc #imm,ccr
+@end smallexample
+@end ifset
+
+@cindex size suffixes, H8/300
+@cindex H8/300 size suffixes
+Four H8/300 instructions (@code{add}, @code{cmp}, @code{mov},
+@code{sub}) are defined with variants using the suffixes @samp{.b},
+@samp{.w}, and @samp{.l} to specify the size of a memory operand.
+@code{@value{AS}} supports these suffixes, but does not require them;
+since one of the operands is always a register, @code{@value{AS}} can
+deduce the correct size.
+
+For example, since @code{r0} refers to a 16-bit register,
+@example
+mov r0,@@foo
+@exdent is equivalent to
+mov.w r0,@@foo
+@end example
+
+If you use the size suffixes, @code{@value{AS}} issues a warning when
+the suffix and the register size do not match.
--- /dev/null
+@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@page
+@node H8/500-Dependent
+@chapter H8/500 Dependent Features
+
+@cindex H8/500 support
+@menu
+* H8/500 Options:: Options
+* H8/500 Syntax:: Syntax
+* H8/500 Floating Point:: Floating Point
+* H8/500 Directives:: H8/500 Machine Directives
+* H8/500 Opcodes:: Opcodes
+@end menu
+
+@node H8/500 Options
+@section Options
+
+@cindex H8/500 options (none)
+@cindex options, H8/500 (none)
+@code{@value{AS}} has no additional command-line options for the Hitachi
+H8/500 family.
+
+@node H8/500 Syntax
+@section Syntax
+
+@menu
+* H8/500-Chars:: Special Characters
+* H8/500-Regs:: Register Names
+* H8/500-Addressing:: Addressing Modes
+@end menu
+
+@node H8/500-Chars
+@subsection Special Characters
+
+@cindex line comment character, H8/500
+@cindex H8/500 line comment character
+@samp{!} is the line comment character.
+
+@cindex line separator, H8/500
+@cindex statement separator, H8/500
+@cindex H8/500 line separator
+@samp{;} can be used instead of a newline to separate statements.
+
+@cindex symbol names, @samp{$} in
+@cindex @code{$} in symbol names
+Since @samp{$} has no special meaning, you may use it in symbol names.
+
+@node H8/500-Regs
+@subsection Register Names
+
+@cindex H8/500 registers
+@cindex registers, H8/500
+You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
+@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, and @samp{r7} to refer to
+the H8/500 registers.
+
+The H8/500 also has these control registers:
+
+@table @code
+@item cp
+code pointer
+
+@item dp
+data pointer
+
+@item bp
+base pointer
+
+@item tp
+stack top pointer
+
+@item ep
+extra pointer
+
+@item sr
+status register
+
+@item ccr
+condition code register
+@end table
+
+All registers are 16 bits long. To represent 32 bit numbers, use two
+adjacent registers; for distant memory addresses, use one of the segment
+pointers (@code{cp} for the program counter; @code{dp} for
+@code{r0}--@code{r3}; @code{ep} for @code{r4} and @code{r5}; and
+@code{tp} for @code{r6} and @code{r7}.
+
+@node H8/500-Addressing
+@subsection Addressing Modes
+
+@cindex addressing modes, H8/500
+@cindex H8/500 addressing modes
+@value{AS} understands the following addressing modes for the H8/500:
+@table @code
+@item R@var{n}
+Register direct
+
+@item @@R@var{n}
+Register indirect
+
+@item @@(d:8, R@var{n})
+Register indirect with 8 bit signed displacement
+
+@item @@(d:16, R@var{n})
+Register indirect with 16 bit signed displacement
+
+@item @@-R@var{n}
+Register indirect with pre-decrement
+
+@item @@R@var{n}+
+Register indirect with post-increment
+
+@item @@@var{aa}:8
+8 bit absolute address
+
+@item @@@var{aa}:16
+16 bit absolute address
+
+@item #@var{xx}:8
+8 bit immediate
+
+@item #@var{xx}:16
+16 bit immediate
+@end table
+
+@node H8/500 Floating Point
+@section Floating Point
+
+@cindex floating point, H8/500 (@sc{ieee})
+@cindex H8/500 floating point (@sc{ieee})
+The H8/500 family has no hardware floating point, but the @code{.float}
+directive generates @sc{ieee} floating-point numbers for compatibility
+with other development tools.
+
+@node H8/500 Directives
+@section H8/500 Machine Directives
+
+@cindex H8/500 machine directives (none)
+@cindex machine directives, H8/500 (none)
+@cindex @code{word} directive, H8/500
+@cindex @code{int} directive, H8/500
+@code{@value{AS}} has no machine-dependent directives for the H8/500.
+However, on this platform the @samp{.int} and @samp{.word} directives
+generate 16-bit numbers.
+
+@node H8/500 Opcodes
+@section Opcodes
+
+@cindex H8/500 opcode summary
+@cindex opcode summary, H8/500
+@cindex mnemonics, H8/500
+@cindex instruction summary, H8/500
+For detailed information on the H8/500 machine instruction set, see
+@cite{H8/500 Series Programming Manual} (Hitachi M21T001).
+
+@code{@value{AS}} implements all the standard H8/500 opcodes. No additional
+pseudo-instructions are needed on this family.
+
+@ifset SMALL
+@c this table, due to the multi-col faking and hardcoded order, looks silly
+@c except in smallbook. See comments below "@set SMALL" near top of this file.
+
+The following table summarizes H8/500 opcodes and their operands:
+
+@c Use @group if it ever works, instead of @page
+@page
+@smallexample
+@i{Legend:}
+abs8 @r{8-bit absolute address}
+abs16 @r{16-bit absolute address}
+abs24 @r{24-bit absolute address}
+crb @r{@code{ccr}, @code{br}, @code{ep}, @code{dp}, @code{tp}, @code{dp}}
+disp8 @r{8-bit displacement}
+ea @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
+ @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16},}
+ @r{@code{#xx:8}, @code{#xx:16}}
+ea_mem @r{@code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
+ @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
+ea_noimm @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
+ @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
+fp r6
+imm4 @r{4-bit immediate data}
+imm8 @r{8-bit immediate data}
+imm16 @r{16-bit immediate data}
+pcrel8 @r{8-bit offset from program counter}
+pcrel16 @r{16-bit offset from program counter}
+qim @r{@code{-2}, @code{-1}, @code{1}, @code{2}}
+rd @r{any register}
+rs @r{a register distinct from rd}
+rlist @r{comma-separated list of registers in parentheses;}
+ @r{register ranges @code{rd-rs} are allowed}
+sp @r{stack pointer (@code{r7})}
+sr @r{status register}
+sz @r{size; @samp{.b} or @samp{.w}. If omitted, default @samp{.w}}
+
+ldc[.b] ea,crb bcc[.w] pcrel16
+ldc[.w] ea,sr bcc[.b] pcrel8
+add[:q] sz qim,ea_noimm bhs[.w] pcrel16
+add[:g] sz ea,rd bhs[.b] pcrel8
+adds sz ea,rd bcs[.w] pcrel16
+addx sz ea,rd bcs[.b] pcrel8
+and sz ea,rd blo[.w] pcrel16
+andc[.b] imm8,crb blo[.b] pcrel8
+andc[.w] imm16,sr bne[.w] pcrel16
+bpt bne[.b] pcrel8
+bra[.w] pcrel16 beq[.w] pcrel16
+bra[.b] pcrel8 beq[.b] pcrel8
+bt[.w] pcrel16 bvc[.w] pcrel16
+bt[.b] pcrel8 bvc[.b] pcrel8
+brn[.w] pcrel16 bvs[.w] pcrel16
+brn[.b] pcrel8 bvs[.b] pcrel8
+bf[.w] pcrel16 bpl[.w] pcrel16
+bf[.b] pcrel8 bpl[.b] pcrel8
+bhi[.w] pcrel16 bmi[.w] pcrel16
+bhi[.b] pcrel8 bmi[.b] pcrel8
+bls[.w] pcrel16 bge[.w] pcrel16
+bls[.b] pcrel8 bge[.b] pcrel8
+@page
+blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem
+blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem
+bgt[.w] pcrel16 movfpe[.b] ea,rd
+bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm
+ble[.w] pcrel16 mulxu sz ea,rd
+ble[.b] pcrel8 neg sz ea
+bclr sz imm4,ea_noimm nop
+bclr sz rs,ea_noimm not sz ea
+bnot sz imm4,ea_noimm or sz ea,rd
+bnot sz rs,ea_noimm orc[.b] imm8,crb
+bset sz imm4,ea_noimm orc[.w] imm16,sr
+bset sz rs,ea_noimm pjmp abs24
+bsr[.b] pcrel8 pjmp @@rd
+bsr[.w] pcrel16 pjsr abs24
+btst sz imm4,ea_noimm pjsr @@rd
+btst sz rs,ea_noimm prtd imm8
+clr sz ea prtd imm16
+cmp[:e][.b] imm8,rd prts
+cmp[:i][.w] imm16,rd rotl sz ea
+cmp[:g].b imm8,ea_noimm rotr sz ea
+cmp[:g][.w] imm16,ea_noimm rotxl sz ea
+Cmp[:g] sz ea,rd rotxr sz ea
+dadd rs,rd rtd imm8
+divxu sz ea,rd rtd imm16
+dsub rs,rd rts
+exts[.b] rd scb/f rs,pcrel8
+extu[.b] rd scb/ne rs,pcrel8
+jmp @@rd scb/eq rs,pcrel8
+jmp @@(imm8,rd) shal sz ea
+jmp @@(imm16,rd) shar sz ea
+jmp abs16 shll sz ea
+jsr @@rd shlr sz ea
+jsr @@(imm8,rd) sleep
+jsr @@(imm16,rd) stc[.b] crb,ea_noimm
+jsr abs16 stc[.w] sr,ea_noimm
+ldm @@sp+,(rlist) stm (rlist),@@-sp
+link fp,imm8 sub sz ea,rd
+link fp,imm16 subs sz ea,rd
+mov[:e][.b] imm8,rd subx sz ea,rd
+mov[:i][.w] imm16,rd swap[.b] rd
+mov[:l][.w] abs8,rd tas[.b] ea
+mov[:l].b abs8,rd trapa imm4
+mov[:s][.w] rs,abs8 trap/vs
+mov[:s].b rs,abs8 tst sz ea
+mov[:f][.w] @@(disp8,fp),rd unlk fp
+mov[:f][.w] rs,@@(disp8,fp) xch[.w] rs,rd
+mov[:f].b @@(disp8,fp),rd xor sz ea,rd
+mov[:f].b rs,@@(disp8,fp) xorc.b imm8,crb
+mov[:g] sz rs,ea_mem xorc.w imm16,sr
+mov[:g] sz ea,rd
+@end smallexample
+@end ifset
--- /dev/null
+@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@page
+@node SH-Dependent
+@chapter Hitachi SH Dependent Features
+
+@cindex SH support
+@menu
+* SH Options:: Options
+* SH Syntax:: Syntax
+* SH Floating Point:: Floating Point
+* SH Directives:: SH Machine Directives
+* SH Opcodes:: Opcodes
+@end menu
+
+@node SH Options
+@section Options
+
+@cindex SH options (none)
+@cindex options, SH (none)
+@code{@value{AS}} has no additional command-line options for the Hitachi
+SH family.
+
+@node SH Syntax
+@section Syntax
+
+@menu
+* SH-Chars:: Special Characters
+* SH-Regs:: Register Names
+* SH-Addressing:: Addressing Modes
+@end menu
+
+@node SH-Chars
+@subsection Special Characters
+
+@cindex line comment character, SH
+@cindex SH line comment character
+@samp{!} is the line comment character.
+
+@cindex line separator, SH
+@cindex statement separator, SH
+@cindex SH line separator
+You can use @samp{;} instead of a newline to separate statements.
+
+@cindex symbol names, @samp{$} in
+@cindex @code{$} in symbol names
+Since @samp{$} has no special meaning, you may use it in symbol names.
+
+@node SH-Regs
+@subsection Register Names
+
+@cindex SH registers
+@cindex registers, SH
+You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
+@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
+@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
+and @samp{r15} to refer to the SH registers.
+
+The SH also has these control registers:
+
+@table @code
+@item pr
+procedure register (holds return address)
+
+@item pc
+program counter
+
+@item mach
+@itemx macl
+high and low multiply accumulator registers
+
+@item sr
+status register
+
+@item gbr
+global base register
+
+@item vbr
+vector base register (for interrupt vectors)
+@end table
+
+@node SH-Addressing
+@subsection Addressing Modes
+
+@cindex addressing modes, SH
+@cindex SH addressing modes
+@code{@value{AS}} understands the following addressing modes for the SH.
+@code{R@var{n}} in the following refers to any of the numbered
+registers, but @emph{not} the control registers.
+
+@table @code
+@item R@var{n}
+Register direct
+
+@item @@R@var{n}
+Register indirect
+
+@item @@-R@var{n}
+Register indirect with pre-decrement
+
+@item @@R@var{n}+
+Register indirect with post-increment
+
+@item @@(@var{disp}, R@var{n})
+Register indirect with displacement
+
+@item @@(R0, R@var{n})
+Register indexed
+
+@item @@(@var{disp}, GBR)
+@code{GBR} offset
+
+@item @@(R0, GBR)
+GBR indexed
+
+@item @var{addr}
+@itemx @@(@var{disp}, PC)
+PC relative address (for branch or for addressing memory). The
+@code{@value{AS}} implementation allows you to use the simpler form
+@var{addr} anywhere a PC relative address is called for; the alternate
+form is supported for compatibility with other assemblers.
+
+@item #@var{imm}
+Immediate data
+@end table
+
+@node SH Floating Point
+@section Floating Point
+
+@cindex floating point, SH (@sc{ieee})
+@cindex SH floating point (@sc{ieee})
+The SH family has no hardware floating point, but the @code{.float}
+directive generates @sc{ieee} floating-point numbers for compatibility
+with other development tools.
+
+@node SH Directives
+@section SH Machine Directives
+
+@cindex SH machine directives (none)
+@cindex machine directives, SH (none)
+@cindex @code{word} directive, SH
+@cindex @code{int} directive, SH
+@code{@value{AS}} has no machine-dependent directives for the SH.
+
+@node SH Opcodes
+@section Opcodes
+
+@cindex SH opcode summary
+@cindex opcode summary, SH
+@cindex mnemonics, SH
+@cindex instruction summary, SH
+For detailed information on the SH machine instruction set, see
+@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).
+
+@code{@value{AS}} implements all the standard SH opcodes. No additional
+pseudo-instructions are needed on this family. Note, however, that
+because @code{@value{AS}} supports a simpler form of PC-relative
+addressing, you may simply write (for example)
+
+@example
+mov.l bar,r0
+@end example
+
+@noindent
+where other assemblers might require an explicit displacement to
+@code{bar} from the program counter:
+
+@example
+mov.l @@(@var{disp}, PC)
+@end example
+
+@ifset SMALL
+@c this table, due to the multi-col faking and hardcoded order, looks silly
+@c except in smallbook. See comments below "@set SMALL" near top of this file.
+
+Here is a summary of SH opcodes:
+
+@page
+@smallexample
+@i{Legend:}
+Rn @r{a numbered register}
+Rm @r{another numbered register}
+#imm @r{immediate data}
+disp @r{displacement}
+disp8 @r{8-bit displacement}
+disp12 @r{12-bit displacement}
+
+add #imm,Rn lds.l @@Rn+,PR
+add Rm,Rn mac.w @@Rm+,@@Rn+
+addc Rm,Rn mov #imm,Rn
+addv Rm,Rn mov Rm,Rn
+and #imm,R0 mov.b Rm,@@(R0,Rn)
+and Rm,Rn mov.b Rm,@@-Rn
+and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
+bf disp8 mov.b @@(disp,Rm),R0
+bra disp12 mov.b @@(disp,GBR),R0
+bsr disp12 mov.b @@(R0,Rm),Rn
+bt disp8 mov.b @@Rm+,Rn
+clrmac mov.b @@Rm,Rn
+clrt mov.b R0,@@(disp,Rm)
+cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
+cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
+cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
+cmp/gt Rm,Rn mov.l Rm,@@-Rn
+cmp/hi Rm,Rn mov.l Rm,@@Rn
+cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
+cmp/pl Rn mov.l @@(disp,GBR),R0
+cmp/pz Rn mov.l @@(disp,PC),Rn
+cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
+div0s Rm,Rn mov.l @@Rm+,Rn
+div0u mov.l @@Rm,Rn
+div1 Rm,Rn mov.l R0,@@(disp,GBR)
+exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
+exts.w Rm,Rn mov.w Rm,@@-Rn
+extu.b Rm,Rn mov.w Rm,@@Rn
+extu.w Rm,Rn mov.w @@(disp,Rm),R0
+jmp @@Rn mov.w @@(disp,GBR),R0
+jsr @@Rn mov.w @@(disp,PC),Rn
+ldc Rn,GBR mov.w @@(R0,Rm),Rn
+ldc Rn,SR mov.w @@Rm+,Rn
+ldc Rn,VBR mov.w @@Rm,Rn
+ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
+ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
+ldc.l @@Rn+,VBR mova @@(disp,PC),R0
+lds Rn,MACH movt Rn
+lds Rn,MACL muls Rm,Rn
+lds Rn,PR mulu Rm,Rn
+lds.l @@Rn+,MACH neg Rm,Rn
+lds.l @@Rn+,MACL negc Rm,Rn
+@page
+nop stc VBR,Rn
+not Rm,Rn stc.l GBR,@@-Rn
+or #imm,R0 stc.l SR,@@-Rn
+or Rm,Rn stc.l VBR,@@-Rn
+or.b #imm,@@(R0,GBR) sts MACH,Rn
+rotcl Rn sts MACL,Rn
+rotcr Rn sts PR,Rn
+rotl Rn sts.l MACH,@@-Rn
+rotr Rn sts.l MACL,@@-Rn
+rte sts.l PR,@@-Rn
+rts sub Rm,Rn
+sett subc Rm,Rn
+shal Rn subv Rm,Rn
+shar Rn swap.b Rm,Rn
+shll Rn swap.w Rm,Rn
+shll16 Rn tas.b @@Rn
+shll2 Rn trapa #imm
+shll8 Rn tst #imm,R0
+shlr Rn tst Rm,Rn
+shlr16 Rn tst.b #imm,@@(R0,GBR)
+shlr2 Rn xor #imm,R0
+shlr8 Rn xor Rm,Rn
+sleep xor.b #imm,@@(R0,GBR)
+stc GBR,Rn xtrct Rm,Rn
+stc SR,Rn
+@end smallexample
+@end ifset
+
+@ifset Hitachi-all
+@ifclear GENERIC
+@raisesections
+@end ifclear
+@end ifset
+
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