freedreno/ir3: rename has_kill to no_earlyz

There are other cases where we need to disable early-z, like image
writes.  So rename to something more generic.

Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 590b9455288cf2fe93e4ee8c40611f1b0d4f274b..f7a68627a4cc06b005c715bf881bb5b18dab57cd 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1395,7 +1395,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                array_insert(ctx->ir, ctx->ir->predicates, kill);
 
                array_insert(b, b->keeps, kill);
-               ctx->so->has_kill = true;
+               ctx->so->no_earlyz = true;
 
                break;
        }

diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index f8aa8522a551b49bd4284b6d8715adafe0feaa76..d598dd76eee8fc94c9d96be884368a7a291a2c2a 100644 (file)
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -431,8 +431,8 @@ struct ir3_shader_variant {
        /* do we have one or more SSBO instructions: */
        bool has_ssbo;
 
-       /* do we have kill instructions: */
-       bool has_kill;
+       /* do we have kill, image write, etc (which prevents early-z): */
+       bool no_earlyz;
 
        /* Layout of constant registers, each section (in vec4). Pointer size
         * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index fc7739b86c228f5b69d64f45790880461c3aaa1b..2df032923cfe5ab1f702bab41908bdad2efdd92d 100644 (file)
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -785,7 +785,7 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
 
    uint32_t gras_su_depth_plane_cntl = 0;
    uint32_t rb_depth_plane_cntl = 0;
-   if (fs->has_kill | fs->writes_pos) {
+   if (fs->no_earlyz | fs->writes_pos) {
       gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
       rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
    }

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index aa787d5ad2d5c8507c85adfa74dbf5a27afa1e8e..029aeba93ef1e0492e9c3e85e62e42b91aab41e3 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -552,7 +552,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
                        val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
                }
-               if (fp->has_kill) {
+               if (fp->no_earlyz) {
                        val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
                }
                if (!ctx->rasterizer->depth_clip_near) {

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 1c3767e2aca8759d7dff8383ab529995264ac207..ec1420da87696317672e37b9d1d2b33cf16aa7f5 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -558,7 +558,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
        if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
                struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
-               bool fragz = fp->has_kill | fp->writes_pos;
+               bool fragz = fp->no_earlyz | fp->writes_pos;
                bool clamp = !ctx->rasterizer->depth_clip_near;
 
                OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
index 25f297cf572253311970bb9a81d4bbd3ebcd5fc8..ce93eee74ad7add4f5f93fa66816872347c0df7d 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
@@ -142,7 +142,7 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
        /* figure out whether we need to disable LRZ write for binning
         * pass using draw pass's fp:
         */
-       emit.no_lrz_write = fp->writes_pos || fp->has_kill;
+       emit.no_lrz_write = fp->writes_pos || fp->no_earlyz;
 
        emit.binning_pass = false;
        emit.dirty = dirty;

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 515d120bb1c0ddb2bee1ba6b26f92ed81fa64c06..bdf590a7e3c7adcf51259eafb6d6fb341b8f1906 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -572,7 +572,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
        if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
                struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
-               bool fragz = fp->has_kill | fp->writes_pos;
+               bool fragz = fp->no_earlyz | fp->writes_pos;
 
                OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
                OUT_RING(ring, zsa->rb_depth_cntl);

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index c049488db0f7929cf5616133cdd4df77e87dd06e..5cd619acc19a067eb58ee8fd2f10324a0b6d383b 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -200,7 +200,7 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
        /* figure out whether we need to disable LRZ write for binning
         * pass using draw pass's fp:
         */
-       emit.no_lrz_write = fp->writes_pos || fp->has_kill;
+       emit.no_lrz_write = fp->writes_pos || fp->no_earlyz;
 
        struct fd_ringbuffer *ring = ctx->batch->draw;
        enum pc_di_primtype primtype = ctx->primtypes[info->mode];

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 13c080e1ddcaf3a6f8e5aa3a644f92bd6a21318d..668b10cccc9426c237854f3001a4d40d70351656 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -614,7 +614,7 @@ setup_stateobj(struct fd_ringbuffer *ring,
        OUT_RING(ring, 0x0000fcfc);   /* VFD_CONTROL_5 */
        OUT_RING(ring, 0x00000000);   /* VFD_CONTROL_6 */
 
-       bool fragz = s[FS].v->has_kill | s[FS].v->writes_pos;
+       bool fragz = s[FS].v->no_earlyz | s[FS].v->writes_pos;
 
        OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
        OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));