i965: add EXT_polygon_offset_clamp support to gen4/gen5

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 3a73c64a88b1e3f5ae956d80e348358984a092fc..2d5abc70cb9cfae6d59b8a9d8e443cb34ae1602d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -223,6 +223,7 @@ brw_upload_clip_prog(struct brw_context *brw)
               /* _NEW_POLYGON, _NEW_BUFFERS */
               key.offset_units = ctx->Polygon.OffsetUnits * ctx->DrawBuffer->_MRD * 2;
               key.offset_factor = ctx->Polygon.OffsetFactor * ctx->DrawBuffer->_MRD;
+              key.offset_clamp = ctx->Polygon.OffsetClamp * ctx->DrawBuffer->_MRD;
            }
 
            if (!ctx->Polygon._FrontBit) {

diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h
index 4e38f2f2ed6a9b5fe811a5756d375ee1064da960..54c76822e224772a1bd148219e77686ce0d202ca 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip.h
+++ b/src/mesa/drivers/dri/i965/brw_clip.h
@@ -62,6 +62,7 @@ struct brw_clip_prog_key {
 
    GLfloat offset_factor;
    GLfloat offset_units;
+   GLfloat offset_clamp;
 };
 
 

diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index 6baf620a1a7782f481430b89b4907ea99fdd04d3..9a4d2a9d6f950805b0b00762e026ab0a00e95d4b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -188,6 +188,12 @@ static void copy_bfc( struct brw_clip_compile *c )
   GLfloat bc   = dir.y * iz;
   offset = ctx->Polygon.OffsetUnits * DEPTH_SCALE;
   offset += MAX2( abs(ac), abs(bc) ) * ctx->Polygon.OffsetFactor;
+  if (ctx->Polygon.OffsetClamp && isfinite(ctx->Polygon.OffsetClamp)) {
+    if (ctx->Polygon.OffsetClamp < 0)
+      offset = MAX2( offset, ctx->Polygon.OffsetClamp );
+    else
+      offset = MIN2( offset, ctx->Polygon.OffsetClamp );
+  }
   offset *= MRD;
 */
 static void compute_offset( struct brw_clip_compile *c )
@@ -211,6 +217,14 @@ static void compute_offset( struct brw_clip_compile *c )
 
    brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor));
    brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units));
+   if (c->key.offset_clamp && isfinite(c->key.offset_clamp)) {
+      brw_CMP(p,
+              vec1(brw_null_reg()),
+              c->key.offset_clamp < 0 ? BRW_CONDITIONAL_GE : BRW_CONDITIONAL_L,
+              vec1(off),
+              brw_imm_f(c->key.offset_clamp));
+      brw_SEL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_clamp));
+   }
 }
 
 

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 546f8fc35fe830628bbcf181641b1afe5bc6d811..0a29a6920162fadb7499a7324b1863335291334a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1457,6 +1457,8 @@ struct brw_context
        */
       drm_intel_bo *multisampled_null_render_target_bo;
       uint32_t fast_clear_op;
+
+      float offset_clamp;
    } wm;
 
    struct {

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7d17edb9023531a5c30f2828789e37a2dc83c1bd..cf6ba5b4aeb5aef4a57e562522f9810c677686bd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -887,14 +887,6 @@ brw_upload_invariant_state(struct brw_context *brw)
    brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
    brw->last_pipeline = BRW_RENDER_PIPELINE;
 
-   if (brw->gen < 6) {
-      /* Disable depth offset clamping. */
-      BEGIN_BATCH(2);
-      OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
-      OUT_BATCH_F(0.0);
-      ADVANCE_BATCH();
-   }
-
    if (brw->gen >= 8) {
       BEGIN_BATCH(3);
       OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2));

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index cd0b56ba60c1a1a2a1007f9019f02c0cd85acd9c..ec54ef2acd9750357e13d7ce795f66a6b1c47be5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -31,6 +31,7 @@
 
 
 
+#include "intel_batchbuffer.h"
 #include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
@@ -251,6 +252,16 @@ brw_upload_wm_unit(struct brw_context *brw)
    }
 
    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
+
+   /* _NEW_POLGYON */
+   if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
+      OUT_BATCH_F(ctx->Polygon.OffsetClamp);
+      ADVANCE_BATCH();
+
+      brw->wm.offset_clamp = ctx->Polygon.OffsetClamp;
+   }
 }
 
 const struct brw_tracked_state brw_wm_unit = {

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 3c77f4773c63f77766115d20384159508d021360..3f9afd16c716e0235d30f5a0d43d8b6929cd1a5e 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -229,6 +229,7 @@ intelInitExtensions(struct gl_context *ctx)
    ctx->Extensions.EXT_packed_float = true;
    ctx->Extensions.EXT_pixel_buffer_object = true;
    ctx->Extensions.EXT_point_parameters = true;
+   ctx->Extensions.EXT_polygon_offset_clamp = true;
    ctx->Extensions.EXT_provoking_vertex = true;
    ctx->Extensions.EXT_stencil_two_side = true;
    ctx->Extensions.EXT_texture_array = true;
@@ -300,7 +301,6 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.AMD_vertex_shader_layer = true;
       ctx->Extensions.EXT_framebuffer_multisample = true;
       ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
-      ctx->Extensions.EXT_polygon_offset_clamp = true;
       ctx->Extensions.EXT_transform_feedback = true;
       ctx->Extensions.OES_depth_texture_cube_map = true;