* m32c-desc.c: Regenerated.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c36d8be18bfecf925e2253e2d31345761adcbd85..5e9bcffbf14be7ea1aecfc1b294e7a942280cf53 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2005-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * m32c-desc.c: Regenerated.
+
 2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
 
        Add ms2.

diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c
index 12b9a1b385ad5b35c91a2bc741f43656e21e4902..5485965cbf36691387b72f122ae764e2f408419d 100644 (file)
--- a/opcodes/m32c-desc.c
+++ b/opcodes/m32c-desc.c
@@ -19263,27 +19263,27 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
 /* not.b:s r0l */
   {
     M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI, "not16.b.s-dst16-3-S-R0l-direct-QI", "not.b:s", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* not.b:s r0h */
   {
     M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, "not16.b.s-dst16-3-S-R0h-direct-QI", "not.b:s", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* not.b:s ${Dsp-8-u8}[sb] */
   {
     M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-SB-relative-QI", "not.b:s", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* not.b:s ${Dsp-8-s8}[fb] */
   {
     M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-FB-relative-QI", "not.b:s", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* not.b:s ${Dsp-8-u16} */
   {
     M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI, "not16.b.s-dst16-3-S-8-16-absolute-QI", "not.b:s", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* not.w${G} $Dst32RnUnprefixedHI */
   {