Merge remote-tracking branch 'origin/xaig' into xc7mux

diff --cc CHANGELOG
Simple merge

diff --cc passes/techmap/abc9.cc
Simple merge

diff --cc techlibs/ecp5/cells_sim.v
Simple merge

diff --cc techlibs/xilinx/abc_xc7.box
index b1c24ed24460b6a1f64f55d6fe6b57da7388d880,6dd71d75875a3bb769f818b7a76a3ce148a73385..7fe8a7236c4b30ccfd2974fda07b573386d89bfc
--- 1/techlibs/xilinx/abc_xc7.box
--- 2/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@@ -23,9 -18,10 +23,10 @@@ MUXF78 3 1 6 
  # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
  # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
  #   (NB: carry chain input/output must be last
- #        input/output and have been moved there
- #        overriding the alphabetical ordering)
+ #        input/output and the entire bus has been
+ #        moved there overriding the otherwise
+ #        alphabetical ordering)
 -CARRY4 3 1 10 8
 +CARRY4 4 1 10 8
  482 -   -   -   -   223 -   -   -   222
  598 407 -   -   -   400 205 -   -   334
  584 556 537 -   -   523 558 226 -   239

diff --cc techlibs/xilinx/cells_sim.v
index 354e4edbff3f93d51d9c9ee5678ec10b7032a32a,4ecf8277be8c40abd5174dd2f4439bc77c2f2a5a..4a1e334d6c2188e4c98bc12056e867e4930dc4f6
--- 1/techlibs/xilinx/cells_sim.v
--- 2/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -289,7 -281,7 +289,7 @@@ module FDPE_1 (output reg Q, input C, C
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
- (* abc_box_id = 5, abc_scc_break="D" *)
 -(* abc_box_id = 4, abc_scc_break="D,WE" *)
++(* abc_box_id = 5, abc_scc_break="D,WE" *)
  module RAM32X1D (
    output DPO, SPO,
    input  D, WCLK, WE,
@@@ -307,7 -299,7 +307,7 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
- (* abc_box_id = 6, abc_scc_break="D" *)
 -(* abc_box_id = 5, abc_scc_break="D,WE" *)
++(* abc_box_id = 6, abc_scc_break="D,WE" *)
  module RAM64X1D (
    output DPO, SPO,
    input  D, WCLK, WE,
@@@ -325,7 -317,7 +325,7 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
- (* abc_box_id = 7, abc_scc_break="D" *)
 -(* abc_box_id = 6, abc_scc_break="D,WE" *)
++(* abc_box_id = 7, abc_scc_break="D,WE" *)
  module RAM128X1D (
    output       DPO, SPO,
    input        D, WCLK, WE,