building microwatt-verilator with external core now works

diff --git a/Makefile b/Makefile
index 509cfdb9e4f866571b2f45bc56619b8843eb7c8e..b061ddb6253aeb3bd75a73b233125b85d1623dc7 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -226,7 +226,7 @@ endif
 
  GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
        -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
-       $(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=$(EXTERNAL_CORE)
+       $(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=true #-gEXTERNAL_CORE=$(EXTERNAL_CORE)
        
 #GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 #      -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
@@ -280,6 +280,9 @@ microwatt-verilator-broken: microwatt.v verilator/microwatt-verilator.cpp verila
        @cp -f obj_dir/microwatt-verilator microwatt-verilator
        
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
+       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+       
+microwatt.v.old: $(synth_files) $(RAM_INIT_FILE)
        $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
        
        

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index b0005ae6bcb82fb60fe029a64c972100c06931f7..1da6b3fb331d04ab7a774c4bfa410ecf70548e9e 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -11,6 +11,7 @@ entity toplevel is
        RAM_INIT_FILE : string   := "firmware.hex";
        RESET_LOW     : boolean  := true;
        SIM_MAIN_BRAM     : boolean  := false;
+       EXTERNAL_CORE     : boolean  := false;
        CLK_INPUT     : positive := 100000000;
        CLK_FREQUENCY : positive := 100000000;
         HAS_FPU       : boolean  := true;
@@ -84,6 +85,7 @@ begin
            RAM_INIT_FILE => RAM_INIT_FILE,
            SIM           => false,
            CLK_FREQ      => CLK_FREQUENCY,
+           EXTERNAL_CORE   => EXTERNAL_CORE,
             HAS_FPU       => HAS_FPU,
             HAS_BTC       => HAS_BTC,
             HAS_SHORT_MULT => HAS_SHORT_MULT,

diff --git a/soc.vhdl b/soc.vhdl
index 77d64565031bf3dce1f721a88c041b2192f1a3e3..65f535fd53f89b17c190455c4a3ccaf4dcbdddc8 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -434,7 +434,7 @@ begin
            dmi_ack => dmi_core_ack,
            dmi_req => dmi_core_req,
            ext_irq => core_ext_irq, --LZ
-           nia_req           => nia_req,
+           nia_req           => nia_req, --FIXME: only when not using extcore
         nia               => nia,
         msr_o             => msr_o,
         insn              => insn,