(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 2084ae9d464d4a342a7a4fab14f5730ec1cc7869..fcdc45a1ade6e580809bc0c506860dca3e4b01b2 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -304,11 +304,11 @@ is not actually a Vector ISA: it is a loop-abstraction-concept that
 is applied *in general* to Scalar operations, just like the x86
 `REP` instruction (if put on steroids).
 
-# EXTRA Pack/Unpack bits
+# Pack/Unpack
 
-The pack/unpack concept of VSX `vpack` is abstracted out as a Sub-Vector
-reordering Schedule.
-Two bits in the `RM` field 
+The pack/unpack concept of VSX `vpack` is abstracted out as Sub-Vector
+reordering.
+Two bits in the `SVSHAPE` [[sv/spr]]
 enable either "packing" or "unpacking"
 on the subvectors vec2/3/4.
 
@@ -331,12 +331,12 @@ In effect the Pack/Unpack performs a Transpose of the subvector elements:
     # yield an outer-SUBVL or inner VL loop with SUBVL
     def index_p(outer):
         if outer:
-            for j in range(SUBVL):
-                for i in range(VL):
+            for j in range(SUBVL):   # subvl is outer
+                for i in range(VL):  # vl is inner
                     yield i+VL*j
         else:
-            for i in range(VL):
-                for j in range(SUBVL):
+            for i in range(VL):        # vl is outer
+                for j in range(SUBVL): # subvl is inner
                     yield i*SUBVL+j
 
      # walk through both source and dest indices simultaneously
@@ -359,18 +359,19 @@ are Sub-elements 2.
      dststep=0  dststep=1  dststep=2
      0   3      1   4      2   5
 
-Setting of both `PACK_en` and `UNPACK_en` is neither prohibited nor
+Setting of both `PACK` and `UNPACK` is neither prohibited nor
 `UNDEFINED` because the reordering is fully deterministic, and
 additional REMAP reordering may be applied. Combined with
 Matrix REMAP this would
 give potentially up to 4 Dimensions of reordering.
 
-Pack/Unpack applies primarily to mv operations, mv.swizzle,
-and some other single-source
-single-destination operations such as Indexed LD/ST and extsw.
-[[sv/mv.swizzle]] has a slightly different pseudocode algorithm
+Pack/Unpack has quirky interactions on 
+[[sv/mv.swizzle]] because it can set a different subvector length for
+destination, and has a slightly different pseudocode algorithm
 for Vertical-First Mode.
 
+Pack/Unpack is enabled (set up) through [[sv/setvl]].
+
 # Reduce modes
 
 Reduction in SVP64 is deterministic and somewhat of a misnomer.  A normal