i965: Gen4-5: Don't enable hardware alpha test with MRT

We have to do this in the shader instead, since these gens lack an
independent RT0 alpha value in their render target write messages.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 6f85f6355cbd7dc25d62c30759dbec944afe0010..53466e714ec8bd1077562f00aeb76a9e58eb4ef7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -187,7 +187,8 @@ static void upload_cc_unit(struct brw_context *brw)
                                eqA != eqRGB);
    }
 
-   if (ctx->Color.AlphaEnabled) {
+   /* _NEW_BUFFERS */
+   if (ctx->Color.AlphaEnabled && ctx->DrawBuffer->_NumColorDrawBuffers <= 1) {
       cc->cc3.alpha_test = 1;
       cc->cc3.alpha_test_func =
         intel_translate_compare_func(ctx->Color.AlphaFunc);