---------- Begin Simulation Statistics ----------
-sim_seconds 2.846145 # Number of seconds simulated
-sim_ticks 2846145040000 # Number of ticks simulated
-final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.846107 # Number of seconds simulated
+sim_ticks 2846106511000 # Number of ticks simulated
+final_tick 2846106511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162017 # Simulator instruction rate (inst/s)
-host_op_rate 196203 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3671761280 # Simulator tick rate (ticks/s)
-host_mem_usage 648900 # Number of bytes of host memory used
-host_seconds 775.14 # Real time elapsed on the host
-sim_insts 125586921 # Number of instructions simulated
-sim_ops 152085297 # Number of ops (including micro ops) simulated
+host_inst_rate 154405 # Simulator instruction rate (inst/s)
+host_op_rate 186958 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3504377822 # Simulator tick rate (ticks/s)
+host_mem_usage 600496 # Number of bytes of host memory used
+host_seconds 812.16 # Real time elapsed on the host
+sim_insts 125401163 # Number of instructions simulated
+sim_ops 151839522 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 8832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1669760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1336112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8514432 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 219648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 604112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 400768 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory
+system.physmem.bytes_read::total 12756096 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1669760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 219648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1889408 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8854144 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8871708 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 138 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 26090 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 21399 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 133038 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 3432 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9459 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 6262 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 199856 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138346 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 142737 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3103 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 586682 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 469453 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2991607 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 495 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 77175 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 212259 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 140813 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4481946 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 586682 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 77175 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 663857 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3110967 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3117138 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3110967 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 586682 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 475610 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.dtb.walker 495 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 77175 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 212273 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7588749 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 199279 # Number of read requests accepted
-system.physmem.writeReqs 179082 # Number of write requests accepted
-system.physmem.readBursts 199279 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 179082 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12747712 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9932032 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12719228 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 11197788 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 23866 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 14978 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 12467 # Per bank write bursts
-system.physmem.perBankRdBursts::1 12549 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12590 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12626 # Per bank write bursts
-system.physmem.perBankRdBursts::4 14976 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12125 # Per bank write bursts
-system.physmem.perBankRdBursts::6 13379 # Per bank write bursts
-system.physmem.perBankRdBursts::7 13505 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12274 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12440 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11813 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11246 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11354 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11924 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11833 # Per bank write bursts
-system.physmem.perBankRdBursts::15 12082 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9603 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9871 # Per bank write bursts
-system.physmem.perBankWrBursts::2 10084 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9904 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9385 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9666 # Per bank write bursts
-system.physmem.perBankWrBursts::6 10609 # Per bank write bursts
-system.physmem.perBankWrBursts::7 10482 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9764 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9386 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9428 # Per bank write bursts
-system.physmem.perBankWrBursts::11 9248 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9294 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9689 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9592 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9183 # Per bank write bursts
+system.physmem.bw_total::total 7599085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 199856 # Number of read requests accepted
+system.physmem.writeReqs 178961 # Number of write requests accepted
+system.physmem.readBursts 199856 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 178961 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12785664 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 5120 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9927488 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 12756096 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 11190044 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 23813 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 14250 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 12367 # Per bank write bursts
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+system.physmem.perBankRdBursts::2 12905 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 15006 # Per bank write bursts
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+system.physmem.perBankWrBursts::15 8821 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 107 # Number of times write queue was full causing retry
-system.physmem.totGap 2846144533500 # Total gap between requests
+system.physmem.numWrRetry 44 # Number of times write queue was full causing retry
+system.physmem.totGap 2846106004500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 551 # Read request sizes (log2)
+system.physmem.readPktSize::2 552 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 198700 # Read request sizes (log2)
+system.physmem.readPktSize::6 199276 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 174691 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 98289 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 174570 # Write request sizes (log2)
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::57 150 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63 536 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 91273 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 248.481807 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 139.408554 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 309.811796 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 47817 52.39% 52.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18099 19.83% 72.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6231 6.83% 79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3556 3.90% 82.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2836 3.11% 86.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1554 1.70% 87.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 946 1.04% 88.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1020 1.12% 89.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9214 10.09% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 91273 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6574 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 30.298296 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 554.918828 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6572 99.97% 99.97% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::samples 90865 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 249.965201 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 140.421700 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 309.995255 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 47261 52.01% 52.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18080 19.90% 71.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6274 6.90% 78.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3625 3.99% 82.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2837 3.12% 85.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1606 1.77% 87.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 998 1.10% 88.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1046 1.15% 89.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 9138 10.06% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 90865 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6548 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 30.509316 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 555.919891 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6546 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 11 0.17% 98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 6 0.09% 98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 17 0.26% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 19 0.29% 99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 5 0.08% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 3 0.05% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.03% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 1 0.02% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 3 0.05% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads
-system.physmem.totQLat 5766362365 # Total ticks spent queuing
-system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6548 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6548 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.689218 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.640113 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 40.676171 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 6193 94.58% 94.58% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::48-63 24 0.37% 96.35% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::96-111 36 0.55% 97.56% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::144-159 17 0.26% 98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 3 0.05% 98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 21 0.32% 98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 18 0.27% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 11 0.17% 99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 3 0.05% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 2 0.03% 99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 5 0.08% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 1 0.02% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 4 0.06% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 1 0.02% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 8 0.12% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 9 0.14% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 3 0.05% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.03% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 3 0.05% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 3 0.05% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::608-623 1 0.02% 99.94% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::912-927 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6548 # Writes before turning the bus around for reads
+system.physmem.totQLat 5702655246 # Total ticks spent queuing
+system.physmem.totMemAccLat 9448455246 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 998880000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28545.25 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 47295.25 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing
-system.physmem.readRowHits 165729 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97368 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes
-system.physmem.avgGap 7522298.90 # Average gap between requests
-system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.569329 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states
+system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing
+system.physmem.readRowHits 166460 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97567 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.89 # Row buffer hit rate for writes
+system.physmem.avgGap 7513142.24 # Average gap between requests
+system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 359425080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 196114875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 815357400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 516060720 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83232319410 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1634649447000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1905662152725 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.569541 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2719260667390 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95037540000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31802228860 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.475203 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states
+system.physmem_1.actEnergy 327514320 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 178703250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 742887600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 489097440 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82208245725 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1635547757250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1905387633825 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.473086 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2720763679724 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95037540000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30305178276 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 33812647 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits
+system.cpu0.branchPred.lookups 20636360 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 13610949 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1051916 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 13187821 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 9315921 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 70.640336 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 3367590 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 213586 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 65253 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 69356 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 69356 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46232 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23124 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 69356 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 69356 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 69356 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 6817 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 9525.708083 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 8414.892081 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 6090.769517 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 6639 97.39% 97.39% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 162 2.38% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 6817 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 5248 76.98% 76.98% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1569 23.02% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6817 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69356 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69356 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6817 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6817 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 76173 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 22995822 # DTB read hits
-system.cpu0.dtb.read_misses 59685 # DTB read misses
-system.cpu0.dtb.write_hits 17147924 # DTB write hits
-system.cpu0.dtb.write_misses 5568 # DTB write misses
+system.cpu0.dtb.read_hits 17307432 # DTB read hits
+system.cpu0.dtb.read_misses 63365 # DTB read misses
+system.cpu0.dtb.write_hits 14534577 # DTB write hits
+system.cpu0.dtb.write_misses 5991 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1432 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1922 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 23055507 # DTB read accesses
-system.cpu0.dtb.write_accesses 17153492 # DTB write accesses
+system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 17370797 # DTB read accesses
+system.cpu0.dtb.write_accesses 14540568 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 40143746 # DTB hits
-system.cpu0.dtb.misses 65253 # DTB misses
-system.cpu0.dtb.accesses 40208999 # DTB accesses
+system.cpu0.dtb.hits 31842009 # DTB hits
+system.cpu0.dtb.misses 69356 # DTB misses
+system.cpu0.dtb.accesses 31911365 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 3866 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 3833 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 9827.457901 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 8615.260983 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5288.530479 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191 893 37.04% 37.04% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1467 60.85% 97.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 9 0.37% 98.26% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.62% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 2111 87.56% 87.56% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 68390761 # ITB inst hits
-system.cpu0.itb.inst_misses 3866 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 38721907 # ITB inst hits
+system.cpu0.itb.inst_misses 3833 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2217 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7269 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses
-system.cpu0.itb.hits 68390761 # DTB hits
-system.cpu0.itb.misses 3866 # DTB misses
-system.cpu0.itb.accesses 68394627 # DTB accesses
-system.cpu0.numCycles 225488562 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 38725740 # ITB inst accesses
+system.cpu0.itb.hits 38721907 # DTB hits
+system.cpu0.itb.misses 3833 # DTB misses
+system.cpu0.itb.accesses 38725740 # DTB accesses
+system.cpu0.numCycles 164661578 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 104715622 # Number of instructions committed
-system.cpu0.committedOps 126599996 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 8092675 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.153342 # CPI: cycles per instruction
-system.cpu0.ipc 0.464394 # IPC: instructions per cycle
+system.cpu0.committedInsts 79519346 # Number of instructions committed
+system.cpu0.committedOps 95696233 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 5042389 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 1874 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5527576937 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.070711 # CPI: cycles per instruction
+system.cpu0.ipc 0.482926 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 2103 # number of quiesce instructions executed
-system.cpu0.tickCycles 187544415 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 37944147 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 678004 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 38699274 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 678516 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 57.035168 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed
+system.cpu0.tickCycles 128007340 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 36654238 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 714687 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 500.798460 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 30351139 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 715199 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 42.437334 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.290770 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947834 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.947834 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.798460 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978122 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.978122 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 80249956 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 80249956 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 21509384 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 21509384 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 16060534 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 16060534 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307394 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 307394 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357644 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 357644 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352742 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 352742 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 37569918 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 37569918 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 37877312 # number of overall hits
-system.cpu0.dcache.overall_hits::total 37877312 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 441440 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 441440 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 555221 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 555221 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131923 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 131923 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20844 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 20844 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21317 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 21317 # number of StoreCondReq misses
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-system.cpu0.dcache.demand_misses::total 996661 # number of demand (read+write) misses
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-system.cpu0.dcache.overall_misses::total 1128584 # number of overall misses
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-system.cpu0.dcache.ReadReq_miss_latency::total 5848521453 # number of ReadReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total 8885926805 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 320729731 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 320729731 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 602000 # number of StoreCondFailReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::total 14734448258 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 14734448258 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 14734448258 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 21950824 # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::total 439317 # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::total 378488 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::total 38566579 # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total 39005896 # number of overall (read+write) accesses
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-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300291 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055072 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055072 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056988 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.025843 # miss rate for demand accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042 # average WriteReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 63691793 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 63691793 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 15776398 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 15776398 # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total 321622 # number of SoftPFReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::total 365571 # number of LoadLockedReq hits
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+system.cpu0.dcache.overall_hits::total 29514134 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 464236 # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::total 577383 # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total 136671 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 21082 # number of LoadLockedReq misses
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total 318010226 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053173 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053173 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.034452 # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total 0.038390 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.670599 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.670599 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15857.060585 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15084.442937 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22404.048081 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22404.048081 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798 # average overall miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 14687.849891 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12984.191936 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12984.191936 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 490183 # number of writebacks
-system.cpu0.dcache.writebacks::total 490183 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69583 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 69583 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243174 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 243174 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14803 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14803 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 312757 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 312757 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 312757 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 312757 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 371857 # number of ReadReq MSHR misses
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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 99536 # number of SoftPFReq MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 783440 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29433 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55598 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4208861714 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4208861714 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses
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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency
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+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31690.708072 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46268.247984 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201758.155106 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185037.100577 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163260.964108 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163260.964108 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183144.010793 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175335.490686 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 661406 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 2715743 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2641226 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 514393 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 305303 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 89358 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43016 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 112820 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 297586 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 284185 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3940361 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2387083 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11736 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174847 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6514027 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126091520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86470884 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17508 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329468 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 212909380 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 677925 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 4032687 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.164340 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.370584 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 3369954 83.57% 83.57% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 662733 16.43% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 4032687 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 2258839735 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 115861999 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 2960687293 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1231161241 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 7364989 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 92493743 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 5430284 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits
+system.cpu1.branchPred.lookups 18540788 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 6039472 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 931744 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 9588411 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 6940637 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 72.385685 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 8266914 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 716215 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 30040 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 26399 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 26399 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19296 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7103 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 26399 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 26399 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 26399 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 2728 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 9779.693548 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 8843.591627 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 5628.626467 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191 924 33.87% 33.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 61.25% 95.12% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575 66 2.42% 97.54% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.13% 99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959 1 0.04% 99.71% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 2728 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1622643264 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1622643264 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1622643264 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 2007 73.57% 73.57% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 721 26.43% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2728 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26399 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26399 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2728 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2728 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 29127 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 5155380 # DTB read hits
-system.cpu1.dtb.read_misses 27847 # DTB read misses
-system.cpu1.dtb.write_hits 4232538 # DTB write hits
-system.cpu1.dtb.write_misses 2193 # DTB write misses
+system.cpu1.dtb.read_hits 10801915 # DTB read hits
+system.cpu1.dtb.read_misses 24746 # DTB read misses
+system.cpu1.dtb.write_hits 6805241 # DTB write hits
+system.cpu1.dtb.write_misses 1653 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 413 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 5183227 # DTB read accesses
-system.cpu1.dtb.write_accesses 4234731 # DTB write accesses
+system.cpu1.dtb.perms_faults 271 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 10826661 # DTB read accesses
+system.cpu1.dtb.write_accesses 6806894 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 9387918 # DTB hits
-system.cpu1.dtb.misses 30040 # DTB misses
-system.cpu1.dtb.accesses 9417958 # DTB accesses
+system.cpu1.dtb.hits 17607156 # DTB hits
+system.cpu1.dtb.misses 26399 # DTB misses
+system.cpu1.dtb.accesses 17633555 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 2268 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 2259 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 2259 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 9888.739946 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 9049.592552 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 4688.260195 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095 127 11.35% 11.35% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 167 14.92% 26.27% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 537 47.99% 74.26% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 96.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 97.32% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 16 1.43% 98.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 11 0.98% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1622052264 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1622052264 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1622052264 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 10199097 # ITB inst hits
-system.cpu1.itb.inst_misses 2268 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 3378 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 39782626 # ITB inst hits
+system.cpu1.itb.inst_misses 2259 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1864 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses
-system.cpu1.itb.hits 10199097 # DTB hits
-system.cpu1.itb.misses 2268 # DTB misses
-system.cpu1.itb.accesses 10201365 # DTB accesses
-system.cpu1.numCycles 54377537 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 39784885 # ITB inst accesses
+system.cpu1.itb.hits 39782626 # DTB hits
+system.cpu1.itb.misses 2259 # DTB misses
+system.cpu1.itb.accesses 39784885 # DTB accesses
+system.cpu1.numCycles 114626006 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 20871299 # Number of instructions committed
-system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.605374 # CPI: cycles per instruction
-system.cpu1.ipc 0.383822 # IPC: instructions per cycle
+system.cpu1.committedInsts 45881817 # Number of instructions committed
+system.cpu1.committedOps 56143289 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 4843481 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 2780 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 5576973220 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.498288 # CPI: cycles per instruction
+system.cpu1.ipc 0.400274 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed
-system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 15657643 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 231595 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 482.666397 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 8898721 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 231963 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 38.362674 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 90493998000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.666397 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942708 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.942708 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 368 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.718750 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 18845353 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 18845353 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 4715534 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 4715534 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 3905905 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3905905 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65439 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 65439 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88128 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 88128 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80091 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 80091 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 8621439 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 8621439 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 8686878 # number of overall hits
-system.cpu1.dcache.overall_hits::total 8686878 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 182965 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 182965 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 168408 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 168408 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35586 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 35586 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17713 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 17713 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23494 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23494 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 351373 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 351373 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 386959 # number of overall misses
-system.cpu1.dcache.overall_misses::total 386959 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2670008756 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2670008756 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4196907972 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 4196907972 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325609985 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 325609985 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550485715 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 550485715 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 359500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 359500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 6866916728 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6866916728 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 6866916728 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6866916728 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 4898499 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 4898499 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 4074313 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 4074313 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101025 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 101025 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105841 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 105841 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103585 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 103585 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 8972812 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 8972812 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 9073837 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 9073837 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037351 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.037351 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041334 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.041334 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.352249 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.352249 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167355 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167355 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226809 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226809 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039160 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.039160 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042646 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.042646 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14593.002793 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14593.002793 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24921.072467 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24921.072467 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18382.543047 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18382.543047 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23430.906402 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23430.906402 # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed
+system.cpu1.tickCycles 97881179 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 16744827 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements 194211 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 472.569028 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 17169326 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 194582 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 88.236970 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 90524286500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.569028 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922986 # Average percentage of cache occupancy
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+system.cpu1.dcache.tags.occ_task_id_blocks::1024 371 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id
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+system.cpu1.dcache.overall_hits::total 16978214 # number of overall hits
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+system.cpu1.dcache.overall_misses::total 332877 # number of overall misses
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+system.cpu1.dcache.LoadLockedReq_miss_latency::total 316145498 # number of LoadLockedReq miss cycles
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+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 527500 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174452 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14691.052395 # average ReadReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17745.850925 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 138038 # number of writebacks
-system.cpu1.dcache.writebacks::total 138038 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18091 # number of ReadReq MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033658 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 117850 # number of writebacks
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13218.242798 # average ReadReq mshr miss latency
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+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24786.549817 # average WriteReq mshr miss latency
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16232.555652 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16415.113795 # average LoadLockedReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882 # average WriteReq mshr uncacheable latency
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3070499 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 597837255 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2221219300 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 913442152 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 3746232198 # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9363750 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205259000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214622750 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754356999 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754356999 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9363750 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959615999 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3968979749 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402779 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080176 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936976 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936976 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955691 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955691 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.482035 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.482035 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101546 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.945769 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.945769 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959958 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959958 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554026 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554026 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104485 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127580 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123653 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.630342 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18504.949162 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39082.755092 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15953.535887 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15953.535887 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15090.519338 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15090.519338 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32217.510128 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32217.510128 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22235.051616 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24846.672490 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150993.426909 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150480.583679 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146980.311578 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146980.311578 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149188.651483 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148913.058530 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 669363 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 1570481 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1215284 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 117850 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 29116 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 76106 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42118 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 86519 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 85085 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 67041 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1897032 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 831140 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7228 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62942 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2798342 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60705024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25653404 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11564 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 86487752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 646083 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1988037 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 1.303225 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.459652 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 1385215 69.68% 69.68% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 602822 30.32% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1988037 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 835355978 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 80571000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 1423456915 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 410007475 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 4338499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 33513487 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30987 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30987 # Transaction distribution
+system.iobus.trans_dist::ReadReq 31003 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31003 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 23198 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
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system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
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system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
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-system.iocache.overall_miss_latency::total 29476377 # number of overall miss cycles
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-system.iocache.ReadReq_avg_miss_latency::total 128717.803493 # average ReadReq miss latency
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182216.999411 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131493.425108 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151981.243176 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144734.739324 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128440.725620 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138465.265498 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164093.594031 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130120.360289 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 145947.321096 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 215059 # Transaction distribution
-system.membus.trans_dist::ReadResp 215059 # Transaction distribution
-system.membus.trans_dist::WriteReq 31175 # Transaction distribution
-system.membus.trans_dist::WriteResp 31175 # Transaction distribution
-system.membus.trans_dist::Writeback 138467 # Transaction distribution
+system.membus.trans_dist::ReadReq 215398 # Transaction distribution
+system.membus.trans_dist::ReadResp 215398 # Transaction distribution
+system.membus.trans_dist::WriteReq 31021 # Transaction distribution
+system.membus.trans_dist::WriteResp 31021 # Transaction distribution
+system.membus.trans_dist::Writeback 138346 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
-system.membus.trans_dist::ReadExReq 39963 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19392 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 76455 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40833 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 14266 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
+system.membus.trans_dist::ReadExReq 39995 # Transaction distribution
+system.membus.trans_dist::ReadExResp 19465 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663047 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 785159 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 894055 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 126068 # Total snoops (count)
-system.membus.snoop_fanout::samples 580884 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19310684 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19503012 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 24138468 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 124155 # Total snoops (count)
+system.membus.snoop_fanout::samples 578323 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 578323 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 580884 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 578323 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88747000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 12490999 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1169123868 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1173969642 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37485233 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 293844 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 516846 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 516831 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31021 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 232833 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 79939 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41160 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 121099 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 51726 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 51726 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083746 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338123 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1421869 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34155096 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5564428 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 39719524 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 288847 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 989795 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.036873 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.188451 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 953298 96.31% 96.31% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36497 3.69% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 989795 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 786931704 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 682239026 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 258695257 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.852840 # Number of seconds simulated
-sim_ticks 2852839554500 # Number of ticks simulated
-final_tick 2852839554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.852796 # Number of seconds simulated
+sim_ticks 2852795541500 # Number of ticks simulated
+final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 169032 # Simulator instruction rate (inst/s)
-host_op_rate 204382 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4294589830 # Simulator tick rate (ticks/s)
-host_mem_usage 620820 # Number of bytes of host memory used
-host_seconds 664.29 # Real time elapsed on the host
-sim_insts 112285680 # Number of instructions simulated
-sim_ops 135768245 # Number of ops (including micro ops) simulated
+host_inst_rate 152327 # Simulator instruction rate (inst/s)
+host_op_rate 184181 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3876544573 # Simulator tick rate (ticks/s)
+host_mem_usage 573860 # Number of bytes of host memory used
+host_seconds 735.91 # Real time elapsed on the host
+sim_insts 112099513 # Number of instructions simulated
+sim_ops 135541235 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1672128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9190636 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10871532 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1672128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1672128 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7983360 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8000884 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 26127 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144125 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 170389 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124740 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129121 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 586128 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3221575 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3810776 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 586128 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 586128 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2798391 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2804533 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2798391 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 586128 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3227717 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6615309 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 170389 # Number of read requests accepted
-system.physmem.writeReqs 165345 # Number of write requests accepted
-system.physmem.readBursts 170389 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 165345 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10897024 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9054784 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10871532 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10319220 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 23835 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4587 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10917 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10861 # Per bank write bursts
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+system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 169771 # Number of read requests accepted
+system.physmem.writeReqs 164823 # Number of write requests accepted
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+system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM
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+system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side
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+system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 37 # Number of times write queue was full causing retry
-system.physmem.totGap 2852839149500 # Total gap between requests
+system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
+system.physmem.totGap 2852795136500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 543 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 169832 # Read request sizes (log2)
+system.physmem.readPktSize::6 169214 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 160964 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 163637 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 61975 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 321.932134 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 188.780856 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 337.844354 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22404 36.15% 36.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14558 23.49% 59.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6628 10.69% 70.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3590 5.79% 76.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2633 4.25% 80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1568 2.53% 82.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1136 1.83% 84.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1187 1.92% 86.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8271 13.35% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61975 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5903 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.841945 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 583.033382 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5902 99.98% 99.98% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::samples 5903 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 23.967644 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.368451 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 42.492651 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::32-47 86 1.46% 95.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 22 0.37% 96.22% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::80-95 26 0.44% 96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 23 0.39% 97.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 23 0.39% 97.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 20 0.34% 98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 7 0.12% 98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 2 0.03% 98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 23 0.39% 98.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 13 0.22% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 11 0.19% 98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 2 0.03% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.03% 99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 3 0.05% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 2 0.03% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 6 0.10% 99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 7 0.12% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 5 0.08% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 2 0.03% 99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 15 0.25% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 4 0.07% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 1 0.02% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 3 0.05% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 1 0.02% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 2 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 2 0.03% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 2 0.03% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5903 # Writes before turning the bus around for reads
-system.physmem.totQLat 1723482630 # Total ticks spent queuing
-system.physmem.totMemAccLat 4915970130 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 851330000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10122.29 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads
+system.physmem.totQLat 1681739444 # Total ticks spent queuing
+system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28872.29 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.62 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.62 # Average write queue length when enqueuing
-system.physmem.readRowHits 140451 # Number of row buffer hits during reads
-system.physmem.writeRowHits 109320 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.25 # Row buffer hit rate for writes
-system.physmem.avgGap 8497319.75 # Average gap between requests
-system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 698123400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 471089520 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83679210810 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1638298500750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1909858967970 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.459893 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2725317218918 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95262440000 # Time in different power states
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
+system.physmem.readRowHits 140075 # Number of row buffer hits during reads
+system.physmem.writeRowHits 109026 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes
+system.physmem.avgGap 8526139.55 # Average gap between requests
+system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.449413 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32255883582 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 223511400 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 121955625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 629943600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 445707360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82264054140 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1639539866250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1909558371015 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.354525 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2727396126418 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95262440000 # Time in different power states
+system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.351340 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30180892082 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 31043514 # Number of BP lookups
-system.cpu.branchPred.condPredicted 16869099 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2536489 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18574786 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13386311 # Number of BTB hits
+system.cpu.branchPred.lookups 31028841 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.067108 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7804422 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1529182 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 65823 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 65823 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43117 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22706 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 65823 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 65823 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 65823 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7829 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 8717.816397 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 7451.711579 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383 6121 78.18% 78.18% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767 1701 21.73% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 66007 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7829 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6444 82.31% 82.31% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1385 17.69% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7829 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65823 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65823 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7829 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7829 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 73652 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24809902 # DTB read hits
-system.cpu.dtb.read_misses 58990 # DTB read misses
-system.cpu.dtb.write_hits 19469042 # DTB write hits
-system.cpu.dtb.write_misses 6833 # DTB write misses
+system.cpu.dtb.read_hits 24765986 # DTB read hits
+system.cpu.dtb.read_misses 59321 # DTB read misses
+system.cpu.dtb.write_hits 19441821 # DTB write hits
+system.cpu.dtb.write_misses 6686 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1238 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 748 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24868892 # DTB read accesses
-system.cpu.dtb.write_accesses 19475875 # DTB write accesses
+system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24825307 # DTB read accesses
+system.cpu.dtb.write_accesses 19448507 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44278944 # DTB hits
-system.cpu.dtb.misses 65823 # DTB misses
-system.cpu.dtb.accesses 44344767 # DTB accesses
+system.cpu.dtb.hits 44207807 # DTB hits
+system.cpu.dtb.misses 66007 # DTB misses
+system.cpu.dtb.accesses 44273814 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 5435 # Table walker walks requested
-system.cpu.itb.walker.walksShort 5435 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 5114 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 5435 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 5435 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 5435 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11172.007540 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 8898.591631 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7073.724538 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191 1308 41.09% 41.09% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383 1159 36.41% 77.51% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575 715 22.46% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 5444 # Table walker walks requested
+system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2873 90.26% 90.26% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3183 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5435 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 5435 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3183 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3183 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 8618 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 57700454 # ITB inst hits
-system.cpu.itb.inst_misses 5435 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 57608448 # ITB inst hits
+system.cpu.itb.inst_misses 5444 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 8445 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 57705889 # ITB inst accesses
-system.cpu.itb.hits 57700454 # DTB hits
-system.cpu.itb.misses 5435 # DTB misses
-system.cpu.itb.accesses 57705889 # DTB accesses
-system.cpu.numCycles 315730000 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 57613892 # ITB inst accesses
+system.cpu.itb.hits 57608448 # DTB hits
+system.cpu.itb.misses 5444 # DTB misses
+system.cpu.itb.accesses 57613892 # DTB accesses
+system.cpu.numCycles 315454477 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 112285680 # Number of instructions committed
-system.cpu.committedOps 135768245 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 7761547 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 112099513 # Number of instructions committed
+system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 5390009685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.811846 # CPI: cycles per instruction
-system.cpu.ipc 0.355638 # IPC: instructions per cycle
+system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 2.814058 # CPI: cycles per instruction
+system.cpu.ipc 0.355359 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
-system.cpu.tickCycles 227805023 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 87924977 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 842413 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.947858 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42688411 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 842925 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 50.643190 # Average number of references to valid blocks.
+system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 842088 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.947858 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 176513094 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 176513094 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23118388 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23118388 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18306742 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18306742 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 356409 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 356409 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 443709 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 443709 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460231 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460231 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41425130 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41425130 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 41781539 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 491811 # number of ReadReq misses
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-system.cpu.dcache.SoftPFReq_misses::total 170067 # number of SoftPFReq misses
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-system.cpu.dcache.LoadLockedReq_misses::total 22347 # number of LoadLockedReq misses
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+system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits
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+system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 460198 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
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-system.cpu.dcache.overall_misses::total 1209707 # number of overall misses
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-system.cpu.dcache.SoftPFReq_accesses::total 526476 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.overall_accesses::total 42991246 # number of overall (read+write) accesses
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system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.649666 # average ReadReq miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.318182 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 697807 # number of writebacks
-system.cpu.dcache.writebacks::total 697807 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74753 # number of ReadReq MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14114 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176238.451909 # average overall mshr uncacheable latency
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-system.cpu.icache.tags.replacements 2897053 # number of replacements
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-system.cpu.icache.overall_avg_miss_latency::total 13559.570342 # average overall miss latency
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
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system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36424 # number of replacements
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
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system.iocache.overall_misses::total 234 # number of overall misses
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system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
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system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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-system.iocache.blocked_cycles::no_mshrs 22431 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3441 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197 # average ReadReq mshr miss latency
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-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 71805 # Transaction distribution
-system.membus.trans_dist::ReadResp 71805 # Transaction distribution
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system.membus.trans_dist::WriteReq 27583 # Transaction distribution
system.membus.trans_dist::WriteResp 27583 # Transaction distribution
-system.membus.trans_dist::Writeback 124740 # Transaction distribution
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system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
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system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 663968 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21354461 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 506 # Total snoops (count)
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1026254667 # Layer occupancy (ticks)
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system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 999643493 # Layer occupancy (ticks)
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system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37473491 # Layer occupancy (ticks)
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system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
projects / gem5.git / commitdiff