--- /dev/null
+# Copyright (c) 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.proxy import *
+
+from Gic import BaseGic
+from KvmVM import KvmVM
+from System import System
+
+class KvmGic(BaseGic):
+ type = 'KvmGic'
+ cxx_header = "arch/arm/kvm/gic.hh"
+
+ dist_addr = Param.Addr(0x1f001000, "Address for distributor")
+ cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
+
+ system = Param.System(Parent.any,
+ 'System this interrupt controller belongs to')
+ kvmVM = Param.KvmVM(Parent.any, 'KVM VM (i.e., shared memory domain)')
import platform
host_isa = platform.machine()
+SimObject('KvmGic.py')
+Source('gic.cc')
+
if host_isa == "armv7l":
SimObject('ArmKvmCPU.py')
Source('arm_cpu.cc')
--- /dev/null
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "arch/arm/kvm/gic.hh"
+
+#include <linux/kvm.h>
+
+#include "debug/Interrupt.hh"
+#include "params/KvmGic.hh"
+
+KvmGic::KvmGic(const KvmGicParams *p)
+ : BaseGic(p),
+ system(*p->system),
+ vm(*p->kvmVM),
+ kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2)),
+ distRange(RangeSize(p->dist_addr, KVM_VGIC_V2_DIST_SIZE)),
+ cpuRange(RangeSize(p->cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
+ addrRanges{distRange, cpuRange}
+{
+ kdev.setAttr<uint64_t>(
+ KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST,
+ p->dist_addr);
+ kdev.setAttr<uint64_t>(
+ KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU,
+ p->cpu_addr);
+}
+
+KvmGic::~KvmGic()
+{
+}
+
+void
+KvmGic::serialize(std::ostream &os)
+{
+ panic("Checkpointing unsupported\n");
+}
+
+void
+KvmGic::unserialize(Checkpoint *cp, const std::string &sec)
+{
+ panic("Checkpointing unsupported\n");
+}
+
+Tick
+KvmGic::read(PacketPtr pkt)
+{
+ panic("KvmGic: PIO from gem5 is currently unsupported\n");
+}
+
+Tick
+KvmGic::write(PacketPtr pkt)
+{
+ panic("KvmGic: PIO from gem5 is currently unsupported\n");
+}
+
+void
+KvmGic::sendInt(uint32_t num)
+{
+ DPRINTF(Interrupt, "Set SPI %d\n", num);
+ setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, true);
+}
+
+void
+KvmGic::clearInt(uint32_t num)
+{
+ DPRINTF(Interrupt, "Clear SPI %d\n", num);
+ setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, false);
+}
+
+void
+KvmGic::sendPPInt(uint32_t num, uint32_t cpu)
+{
+ DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
+ setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, true);
+}
+
+void
+KvmGic::clearPPInt(uint32_t num, uint32_t cpu)
+{
+ DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
+ setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, false);
+}
+
+void
+KvmGic::verifyMemoryMode() const
+{
+ if (!(system.isAtomicMode() && system.bypassCaches())) {
+ fatal("The in-kernel KVM GIC can only be used with KVM CPUs, but the "
+ "current memory mode does not support KVM.\n");
+ }
+}
+
+void
+KvmGic::setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high)
+{
+ assert(type < KVM_ARM_IRQ_TYPE_MASK);
+ assert(vcpu < KVM_ARM_IRQ_VCPU_MASK);
+ assert(irq < KVM_ARM_IRQ_NUM_MASK);
+ const uint32_t line(
+ (type << KVM_ARM_IRQ_TYPE_SHIFT) |
+ (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
+ (irq << KVM_ARM_IRQ_NUM_SHIFT));
+
+ vm.setIRQLine(line, high);
+}
+
+
+KvmGic *
+KvmGicParams::create()
+{
+ return new KvmGic(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#ifndef __ARCH_ARM_KVM_GIC_HH__
+#define __ARCH_ARM_KVM_GIC_HH__
+
+#include "arch/arm/system.hh"
+#include "cpu/kvm/device.hh"
+#include "cpu/kvm/vm.hh"
+#include "dev/arm/base_gic.hh"
+#include "dev/platform.hh"
+
+class KvmGicParams;
+
+/**
+ * In-kernel GIC model.
+ *
+ * When using a KVM-based CPU model, it is possible to offload GIC
+ * emulation to the kernel. This reduces some overheads when the guest
+ * accesses the GIC and makes it possible to use in-kernel
+ * architected/generic timer emulation.
+ *
+ * This device uses interfaces with the kernel GicV2 model that is
+ * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
+ * Linux kernel sources.
+ *
+ * This GIC model has the following known limitations:
+ * <ul>
+ * <li>Checkpointing is not supported.
+ * <li>This model only works with kvm. Simulated CPUs are not
+ * supported since this would require the kernel to inject
+ * interrupt into the simulated CPU.
+ * </ul>
+ *
+ * @warn This GIC model cannot be used with simulated CPUs!
+ */
+class KvmGic : public BaseGic
+{
+ public: // SimObject / Serializable / Drainable
+ KvmGic(const KvmGicParams *p);
+ ~KvmGic();
+
+ void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+ void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+
+ void serialize(std::ostream &os) M5_ATTR_OVERRIDE;
+ void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
+
+ public: // PioDevice
+ AddrRangeList getAddrRanges() const { return addrRanges; }
+ Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+
+ public: // BaseGic
+ void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
+ void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
+
+ void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+ void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+
+ protected:
+ /**
+ * Do memory mode sanity checks
+ *
+ * This method only really exists to warn users that try to switch
+ * to a simulate CPU. There is no fool proof method to detect
+ * simulated CPUs, but checking that we're in atomic mode and
+ * bypassing caches should be robust enough.
+ */
+ void verifyMemoryMode() const;
+
+ /**
+ * Update the kernel's VGIC interrupt state
+ *
+ * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI)
+ * @param vcpu CPU id within KVM (ignored for SPIs)
+ * @param irq Interrupt number
+ * @param high True to signal an interrupt, false to clear it.
+ */
+ void setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high);
+
+ /** System this interrupt controller belongs to */
+ System &system;
+ /** VM for this system */
+ KvmVM &vm;
+ /** Kernel interface to the GIC */
+ KvmDevice kdev;
+
+ /** Address range for the distributor interface */
+ const AddrRange distRange;
+ /** Address range for the CPU interfaces */
+ const AddrRange cpuRange;
+ /** Union of all memory */
+ const AddrRangeList addrRanges;
+};
+
+#endif // __ARCH_ARM_KVM_GIC_HH__
SimObject('BaseKvmCPU.py')
Source('base.cc')
+ Source('device.cc')
Source('vm.cc')
Source('perfevent.cc')
Source('timer.cc')
--- /dev/null
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "cpu/kvm/device.hh"
+
+#include <linux/kvm.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+#include <cassert>
+#include <cerrno>
+
+#include "base/misc.hh"
+
+KvmDevice::KvmDevice(int _fd)
+ : fd(_fd)
+{
+}
+
+KvmDevice::~KvmDevice()
+{
+ close(fd);
+}
+
+void
+KvmDevice::getAttrPtr(uint32_t group, uint64_t attr, void *data) const
+{
+#ifdef KVM_GET_DEVICE_ATTR
+ struct kvm_device_attr dattr = {
+ 0, // Flags
+ group,
+ attr,
+ reinterpret_cast<uint64_t>(data),
+ };
+
+ if (ioctl(KVM_GET_DEVICE_ATTR, &dattr) == -1) {
+ panic("Failed to get attribute (group: %i, attr: %i, errno: %i)",
+ group, attr, errno);
+ }
+#else
+ panic("Kernel headers don't support KVM_GET_DEVICE_ATTR\n");
+#endif
+}
+
+void
+KvmDevice::setAttrPtr(uint32_t group, uint64_t attr, const void *data) const
+{
+#ifdef KVM_SET_DEVICE_ATTR
+ struct kvm_device_attr dattr = {
+ 0, // Flags
+ group,
+ attr,
+ reinterpret_cast<uint64_t>(data),
+ };
+
+ if (ioctl(KVM_SET_DEVICE_ATTR, &dattr) == -1) {
+ panic("Failed to set attribute (group: %i, attr: %i, errno: %i)",
+ group, attr, errno);
+ }
+#else
+ panic("Kernel headers don't support KVM_GET_DEVICE_ATTR\n");
+#endif
+}
+
+bool
+KvmDevice::hasAttr(uint32_t group, uint64_t attr) const
+{
+#ifdef KVM_HAS_DEVICE_ATTR
+ struct kvm_device_attr dattr = {
+ 0, // Flags
+ group,
+ attr,
+ 0, // Data address (ignored)
+ };
+
+ return ioctl(KVM_HAS_DEVICE_ATTR, &dattr) == 0;
+#else
+ panic("Kernel headers don't support KVM_HAS_DEVICE_ATTR\n");
+#endif
+}
+
+int
+KvmDevice::ioctl(int request, long p1) const
+{
+ assert(fd != -1);
+
+ return ::ioctl(fd, request, p1);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#ifndef __CPU_KVM_DEVICE_HH__
+#define __CPU_KVM_DEVICE_HH__
+
+#include <cstdint>
+
+/**
+ * KVM device wrapper
+ *
+ * This is a wrapper around a device emulated by KVM. Such devices can
+ * be created using KvmVM::createDevice() API. They are typically used
+ * for in-kernel interrupt controllers and similar devices.
+ *
+ * Each device has a device-specific set of attributes which are
+ * mapped into groups. The available attributes are described in the
+ * device's documentation in the kernel source tree
+ * (Documentation/virtual/kvm/devices/). Each attribute can be
+ * accessed with the getAttr() and setAttr() access methods. The
+ * presence of an attribute can be queried using the hasAttr() method.
+ */
+class KvmDevice
+{
+ public:
+ KvmDevice(int fd);
+ virtual ~KvmDevice();
+
+ public:
+ /**
+ * Get the value of an attribute
+ *
+ * See KVM's documentation, and specifically the device-specific
+ * documentation, for available attributes and attribute groups.
+ *
+ * @param group Attribute group
+ * @param attr Attribute ID within group
+ * @return Attribute value
+ */
+ template<typename T>
+ T getAttr(uint32_t group, uint64_t attr) const {
+ T data;
+ getAttrPtr(group, attr, &data);
+ return data;
+ }
+
+ /**
+ * Get the value of an attribute
+ *
+ * See KVM's documentation, and specifically the device-specific
+ * documentation, for available attributes and attribute groups.
+ *
+ * @param group Attribute group
+ * @param attr Attribute ID within group
+ * @return Attribute value
+ */
+ template<typename T>
+ void setAttr(uint32_t group, uint64_t attr, const T &data) const {
+ setAttrPtr(group, attr, &data);
+ }
+
+ void getAttrPtr(uint32_t group, uint64_t attr, void *data) const;
+ void setAttrPtr(uint32_t group, uint64_t attr, const void *data) const;
+
+ /**
+ * Check if a device attribute is valid
+ *
+ * See KVM's documentation, and specifically the device-specific
+ * documentation, for available attributes and attribute groups.
+ *
+ * @param group Attribute group
+ * @param attr Attribute ID within group
+ * @return true if attribute is valid, false otherwise.
+ */
+ bool hasAttr(uint32_t group, uint64_t attr) const;
+
+ protected:
+ int ioctl(int request, long p1) const;
+ int ioctl(int request, void *p1) const {
+ return ioctl(request, (long)p1);
+ }
+ int ioctl(int request) const {
+ return ioctl(request, 0L);
+ }
+
+ private:
+ int fd;
+};
+
+#endif // __CPU_KVM_DEVICE_HH__
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
errno);
}
+int
+KvmVM::createDevice(uint32_t type, uint32_t flags)
+{
+#if defined(KVM_CREATE_DEVICE)
+ struct kvm_create_device dev = { type, 0, flags };
+
+ if (ioctl(KVM_CREATE_DEVICE, &dev) == -1) {
+ panic("KVM: Failed to create device (errno: %i)\n",
+ errno);
+ }
+
+ return dev.fd;
+#else
+ panic("Kernel headers don't support KVM_CREATE_DEVICE\n");
+#endif
+}
+
int
KvmVM::createVCPU(long vcpuID)
{
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
*/
void freeMemSlot(const MemSlot slot);
+ /**
+ * Create an in-kernel device model.
+ *
+ * @param type Device type (KVM_DEV_TYPE_xxx)
+ * @param flags Creation flags (KVM_CREATE_DEVICE_xxx)
+ * @return Device file descriptor
+ */
+ int createDevice(uint32_t type, uint32_t flags = 0);
+
/** Global KVM interface */
Kvm kvm;
projects / gem5.git / commitdiff