boards:
Provides platforms and targets for the supported boards. All Migen's platforms
- can also be used in LiteX.
+ can also be used in LiteX. The boards present in the LiteX repository are the
+ official ones that are used for development/CI. More boards are available at:
+ https://github.com/litex-hub/litex-boards
[> Very Quick start guide (for newcomers)
-----------------------------------------
+++ /dev/null
-# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
-
-# IOs ----------------------------------------------------------------------------------------------
-
-_io = [
- ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
- ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
- ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
- ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
-
- ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
-
- ("clk200", 0,
- Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
- Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
- ),
-
- ("clk156", 0,
- Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
- Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
- ),
-
- ("serial", 0,
- Subsignal("cts", Pins("V19")),
- Subsignal("rts", Pins("W19")),
- Subsignal("tx", Pins("U19")),
- Subsignal("rx", Pins("T19")),
- IOStandard("LVCMOS18")
- ),
-
- ("eth_clocks", 0,
- Subsignal("tx", Pins("U22")),
- Subsignal("rx", Pins("U21")),
- IOStandard("LVCMOS18")
- ),
-
- ("eth", 0,
- Subsignal("rx_ctl", Pins("U14")),
- Subsignal("rx_data", Pins("U17 V17 V16 V14")),
- Subsignal("tx_ctl", Pins("T15")),
- Subsignal("tx_data", Pins("U16 U15 T18 T17")),
- Subsignal("rst_n", Pins("V18")),
- Subsignal("mdc", Pins("W18")),
- Subsignal("mdio", Pins("T14")),
- IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
- ),
-
-
- ("ddram", 0,
- Subsignal("a", Pins(
- "M4 J3 J1 L4 K5 M7 K1 M6",
- "H1 K3 N7 L5 L7 N6 L3 K2"),
- IOStandard("SSTL15")),
- Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
- Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
- Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
- Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
- Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
- Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
- IOStandard("SSTL15")),
- Subsignal("dq", Pins(
- "AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
- "AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
- "AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
- "Y3 W3 W6 V6 W4 W5 W1 V1",
- "G2 D1 E1 E2 F2 A2 A3 C2",
- "C3 D3 A4 B4 C4 D4 D5 E5",
- "F4 G4 K6 K7 K8 L8 J5 J6",
- "G6 H6 F7 F8 G8 H8 D6 E6"),
- IOStandard("SSTL15")),
- Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
- IOStandard("DIFF_SSTL15")),
- Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
- IOStandard("DIFF_SSTL15")),
- Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
- Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
- Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
- Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
- Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
- ),
-
- ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
-
- ("gtp_refclk", 0,
- Subsignal("p", Pins("AA13")),
- Subsignal("n", Pins("AB13"))
- ),
-
- ("sfp", 0,
- Subsignal("txp", Pins("AC10")),
- Subsignal("txn", Pins("AD10")),
- Subsignal("rxp", Pins("AC12")),
- Subsignal("rxn", Pins("AD12")),
- ),
- ("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
- ("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
- ("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
- ("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
-]
-
-# Connectors ---------------------------------------------------------------------------------------
-
-_connectors = [
- ("HPC", {
- "CLK0_M2C_N": "C19",
- "CLK0_M2C_P": "D19",
- "CLK1_M2C_N": "H22",
- "CLK1_M2C_P": "H21",
- "LA00_CC_N": "C18",
- "LA00_CC_P": "D18",
- "LA01_CC_N": "E18",
- "LA01_CC_P": "E17",
- "LA02_N": "H15",
- "LA02_P": "H14",
- "LA03_N": "F17",
- "LA03_P": "G17",
- "LA04_N": "F19",
- "LA04_P": "F18",
- "LA05_N": "F15",
- "LA05_P": "G15",
- "LA06_N": "F20",
- "LA06_P": "G19",
- "LA07_N": "G16",
- "LA07_P": "H16",
- "LA08_N": "B17",
- "LA08_P": "C17",
- "LA09_N": "D16",
- "LA09_P": "E16",
- "LA10_N": "A18",
- "LA10_P": "A17",
- "LA11_N": "A19",
- "LA11_P": "B19",
- "LA12_N": "D20",
- "LA12_P": "E20",
- "LA13_N": "A20",
- "LA13_P": "B20",
- "LA14_N": "B21",
- "LA14_P": "C21",
- "LA15_N": "A22",
- "LA15_P": "B22",
- "LA16_N": "D21",
- "LA16_P": "E21",
- "LA17_CC_N": "J21",
- "LA17_CC_P": "K21",
- "LA18_CC_N": "G21",
- "LA18_CC_P": "G20",
- "LA19_N": "L14",
- "LA19_P": "M14",
- "LA20_N": "M17",
- "LA20_P": "M16",
- "LA21_N": "H19",
- "LA21_P": "J19",
- "LA22_N": "L18",
- "LA22_P": "L17",
- "LA23_N": "J20",
- "LA23_P": "K20",
- "LA24_N": "H18",
- "LA24_P": "J18",
- "LA25_N": "F22",
- "LA25_P": "G22",
- "LA26_N": "H24",
- "LA26_P": "J24",
- "LA27_N": "E23",
- "LA27_P": "F23",
- "LA28_N": "K23",
- "LA28_P": "K22",
- "LA29_N": "F24",
- "LA29_P": "G24",
- "LA30_N": "D25",
- "LA30_P": "E25",
- "LA31_N": "D26",
- "LA31_P": "E26",
- "LA32_N": "G26",
- "LA32_P": "H26",
- "LA33_N": "F25",
- "LA33_P": "G25",
- "PRSNT_M2C_L": "N16",
- "PWR_GOOD_FLASH_RST_B": "P15"}
- ),
- ("XADC", {
- "GPIO0": "H17",
- "GPIO1": "E22",
- "GPIO2": "K18",
- "GPIO3": "L19",
- "VAUX0_N": "J16",
- "VAUX0_P": "K15",
- "VAUX8_N": "J15",
- "VAUX8_P": "J14",
- }
- ),
-]
-
-# Platform -----------------------------------------------------------------------------------------
-
-class Platform(XilinxPlatform):
- default_clk_name = "clk156"
- default_clk_period = 6.4
-
- def __init__(self):
- XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
- self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
- self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
-
- def create_programmer(self):
- return VivadoProgrammer()
-
- def do_finalize(self, fragment):
- XilinxPlatform.do_finalize(self, fragment)
- try:
- self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
- except ConstraintError:
- pass
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
- except ConstraintError:
- pass
- try:
- self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
- except ConstraintError:
- pass
+++ /dev/null
-# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.altera import AlteraPlatform
-from litex.build.altera.programmer import USBBlaster
-
-
-_io = [
- ("clk10", 0, Pins("N5"), IOStandard("3.3-V LVTTL")),
- ("clk50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")),
- ("clk50", 1, Pins("N14"), IOStandard("3.3-V LVTTL")),
-
- ("serial", 0,
- Subsignal("tx", Pins("V10"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
- Subsignal("rx", Pins("W10"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
- ),
-
- ("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")),
- ("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")),
- ("user_led", 2, Pins("A10"), IOStandard("3.3-V LVTTL")),
- ("user_led", 3, Pins("B10"), IOStandard("3.3-V LVTTL")),
- ("user_led", 4, Pins("D13"), IOStandard("3.3-V LVTTL")),
- ("user_led", 5, Pins("C13"), IOStandard("3.3-V LVTTL")),
- ("user_led", 6, Pins("E14"), IOStandard("3.3-V LVTTL")),
- ("user_led", 7, Pins("D14"), IOStandard("3.3-V LVTTL")),
- ("user_led", 8, Pins("A11"), IOStandard("3.3-V LVTTL")),
- ("user_led", 9, Pins("B11"), IOStandard("3.3-V LVTTL")),
-
- ("user_btn", 0, Pins("B8"), IOStandard("3.3-V LVTTL")),
- ("user_btn", 1, Pins("A7"), IOStandard("3.3-V LVTTL")),
-
- ("user_sw", 0, Pins("C10"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 1, Pins("C11"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 2, Pins("D12"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 3, Pins("C12"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 4, Pins("A12"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 5, Pins("B12"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 6, Pins("A13"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 7, Pins("A14"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 8, Pins("B14"), IOStandard("3.3-V LVTTL")),
- ("user_sw", 9, Pins("F15"), IOStandard("3.3-V LVTTL")),
-
- # 7-segment displays
- ("seven_seg", 0, Pins("C14 E15 C15 C16 E16 D17 C17 D15"), IOStandard("3.3-V LVTTL")),
- ("seven_seg", 1, Pins("C18 D18 E18 B16 A17 A18 B17 A16"), IOStandard("3.3-V LVTTL")),
- ("seven_seg", 2, Pins("B20 A20 B19 A21 B21 C22 B22 A19"), IOStandard("3.3-V LVTTL")),
- ("seven_seg", 3, Pins("F21 E22 E21 C19 C20 D19 E17 D22"), IOStandard("3.3-V LVTTL")),
- ("seven_seg", 4, Pins("F18 E20 E19 J18 H19 F19 F20 F17"), IOStandard("3.3-V LVTTL")),
- ("seven_seg", 5, Pins("J20 K20 L18 N18 M20 N19 N20 L19"), IOStandard("3.3-V LVTTL")),
-
-
- ("gpio_0", 0,
- Pins("V10 W10 V9 W9 V8 W8 V7 W7 W6 V5 W5 AA15 AA14 W13 W12 AB13 AB12 Y11 AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7 AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3 AB2 AA2"),
- IOStandard("3.3-V LVTTL")
- ),
- ("gpio_1", 0,
- Pins("AB5 AB6 AB7 AB8 AB9 Y10 AA11 AA12 AB17 AA17 AB19 AA19 Y19 AB20 AB21 AA20 F16"),
- IOStandard("3.3-V LVTTL")
- ),
-
- ("vga_out", 0,
- Subsignal("hsync_n", Pins("N3")),
- Subsignal("vsync_n", Pins("N1")),
- Subsignal("r", Pins("AA1 V1 Y2 Y1")),
- Subsignal("g", Pins("W1 T2 R2 R1")),
- Subsignal("b", Pins("P1 T1 P4 N2")),
- IOStandard("3.3-V LVTTL")
- ),
-
- ("sdram_clock", 0, Pins("L14"), IOStandard("3.3-V LVTTL")),
- ("sdram", 0,
- Subsignal("a", Pins("U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20")),
- Subsignal("ba", Pins("T21 T22")),
- Subsignal("cs_n", Pins("U20")),
- Subsignal("cke", Pins("N22")),
- Subsignal("ras_n", Pins("U22")),
- Subsignal("cas_n", Pins("U21")),
- Subsignal("we_n", Pins("V20")),
- Subsignal("dq", Pins("Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22")),
- Subsignal("dm", Pins("V22 J21")),
- IOStandard("3.3-V LVTTL")
- ),
-
- ("accelerometer", 0,
- Subsignal("int1", Pins("Y14")),
- Subsignal("int1", Pins("Y13")),
- Subsignal("mosi", Pins("V11")),
- Subsignal("miso", Pins("V12")),
- Subsignal("clk", Pins("AB15")),
- Subsignal("cs_n", Pins("AB16")),
- IOStandard("3.3-V LVTTL")
- )
-]
-
-
-class Platform(AlteraPlatform):
- default_clk_name = "clk50"
- default_clk_period = 20
- create_rbf = False
-
- def __init__(self):
- AlteraPlatform.__init__(self, "10M50DAF484C7G", _io)
-
- def create_programmer(self):
- return USBBlaster()
+++ /dev/null
-# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.altera import AlteraPlatform
-
-# IOs ------------------------------------------------------------------
-
-_io = [
- ("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
-
- ("serial", 0,
- Subsignal("tx", Pins("AC18"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
- Subsignal("rx", Pins("Y17"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
- ),
-
- ("sdram_clock", 0, Pins("AH12"), IOStandard("3.3-V LVTTL")),
- ("sdram", 0,
- Subsignal("a", Pins("AK14 AH14 AG15 AE14 AB15 AC14 AD14 AF15 AH15 AG13 AG12 AH13 AJ14")),
- Subsignal("ba", Pins("AF13 AJ12")),
- Subsignal("cs_n", Pins("AG11")),
- Subsignal("cke", Pins("AK13")),
- Subsignal("ras_n", Pins("AE13")),
- Subsignal("cas_n", Pins("AF11")),
- Subsignal("we_n", Pins("AA13")),
- Subsignal("dq", Pins("AK6 AJ7 AK7 AK8 AK9 AG10 AK11 AJ11 AH10 AJ10 AJ9 AH9 AH8 AH7 AJ6 AJ5")),
- Subsignal("dm", Pins("AB13 AK12")),
- IOStandard("3.3-V LVTTL")
- ),
-]
-
-# Platform -------------------------------------------------------------
-
-class Platform(AlteraPlatform):
- default_clk_name = "clk50"
- default_clk_period = 20
-
- def __init__(self):
- AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)
+++ /dev/null
-# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.altera import AlteraPlatform
-
-# IOs ------------------------------------------------------------------
-
-_io = [
- ("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")),
-
- ("serial", 0,
- Subsignal("tx", Pins("AB22"), IOStandard("3.3-V LVTTL")), # JP5 GPIO[0]
- Subsignal("rx", Pins("AC15"), IOStandard("3.3-V LVTTL")) # JP5 GPIO[1]
- ),
-
- ("sdram_clock", 0, Pins("AE5"), IOStandard("3.3-V LVTTL")),
- ("sdram", 0,
- Subsignal("a", Pins("R6 V8 U8 P1 V5 W8 W7 AA7 Y5 Y6 R5 AA5 Y7")),
- Subsignal("ba", Pins("U7 R4")),
- Subsignal("cs_n", Pins("T4")),
- Subsignal("cke", Pins("AA6")),
- Subsignal("ras_n", Pins("U6")),
- Subsignal("cas_n", Pins("V7")),
- Subsignal("we_n", Pins("V6")),
- Subsignal("dq", Pins("W3 W2 V4 W1 V3 V2 V1 U3 Y3 Y4 AB1 AA3 AB2 AC1 AB3 AC2")),
- Subsignal("dm", Pins("U2 W4")),
- IOStandard("3.3-V LVTTL")
- ),
-]
-
-# Platform -------------------------------------------------------------
-
-class Platform(AlteraPlatform):
- default_clk_name = "clk50"
- default_clk_period = 20
-
- def __init__(self):
- AlteraPlatform.__init__(self, "EP4CE115F29C7", _io)
-# This file is Copyright (c) 2018 Felix Held <felix-github@felixheld.de>
# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
+++ /dev/null
-# This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
-# License: BSD
-
-
-from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, iMPACT
-
-_io = [
- ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")),
- ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")),
- ("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")),
- ("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")),
-
- ("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")),
- ("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")),
- ("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")),
- ("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")),
-
- ("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")),
-
- ("serial", 0,
- Subsignal("cts", Pins("F19")),
- Subsignal("rts", Pins("F18")),
- Subsignal("tx", Pins("B21")),
- Subsignal("rx", Pins("H17")),
- IOStandard("LVCMOS25")
- ),
-
- ("clk200", 0,
- Subsignal("p", Pins("K21")),
- Subsignal("n", Pins("K22")),
- IOStandard("LVDS_25")
- ),
-
- ("eth_clocks", 0,
- # Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode
- Subsignal("gtx", Pins("AB7")),
- Subsignal("rx", Pins("P20")),
- IOStandard("LVCMOS25")
- ),
- ("eth", 0,
- Subsignal("rst_n", Pins("J22")),
- Subsignal("int_n", Pins("J20")),
- Subsignal("mdio", Pins("V20")),
- Subsignal("mdc", Pins("R19")),
- Subsignal("rx_dv", Pins("T22")),
- Subsignal("rx_er", Pins("U20")),
- Subsignal("rx_data", Pins("P19 Y22 Y21 W22 W20 V22 V21 U22")),
- Subsignal("tx_en", Pins("T8")),
- Subsignal("tx_er", Pins("U8")),
- Subsignal("tx_data", Pins("U10 T10 AB8 AA8 AB9 Y9 Y12 W12")),
- Subsignal("col", Pins("M16")),
- Subsignal("crs", Pins("N15")),
- IOStandard("LVCMOS25")
- ),
-]
-
-_connectors = [
- ("LPC", {
- "DP0_C2M_P": "B16",
- "DP0_C2M_N": "A16",
- "DP0_M2C_P": "D15",
- "DP0_M2C_N": "C15",
- "LA06_P": "D4",
- "LA06_N": "D5",
- "LA10_P": "H10",
- "LA10_N": "H11",
- "LA14_P": "C17",
- "LA14_N": "A17",
- "LA18_CC_P": "T12",
- "LA18_CC_N": "U12",
- "LA27_P": "AA10",
- "LA27_N": "AB10",
- "IIC_SCL_MAIN": "T21",
- "IIC_SDA_MAIN": "R22",
- "CLK1_M2C_P": "E16",
- "CLK1_M2C_N": "F16",
- "LA00_CC_P": "G9",
- "LA00_CC_N": "F10",
- "LA03_P": "B18",
- "LA03_N": "A18",
- "LA08_P": "B20",
- "LA08_N": "A20",
- "LA12_P": "H13",
- "LA12_N": "G13",
- "LA16_P": "C5",
- "LA16_N": "A5",
- "GBTCLK0_M2C_P": "E12",
- "GBTCLK0_M2C_N": "F12",
- "LA01_CC_P": "F14",
- "LA01_CC_N": "F15",
- "LA05_P": "C4",
- "LA05_N": "A4",
- "LA09_P": "F7",
- "LA09_N": "F8",
- "LA13_P": "G16",
- "LA13_N": "F17",
- "LA17_CC_P": "Y11",
- "LA17_CC_N": "AB11",
- "LA23_P": "U9",
- "LA23_N": "V9",
- "LA26_P": "U14",
- "LA26_N": "U13",
- "PRSNT_M2C_L": "Y16",
- "CLK0_M2C_P": "H12",
- "CLK0_M2C_N": "G11",
- "LA02_P": "G8",
- "LA02_N": "F9",
- "LA04_P": "C19",
- "LA04_N": "A19",
- "LA07_P": "B2",
- "LA07_N": "A2",
- "LA11_P": "H14",
- "LA11_N": "G15",
- "LA15_P": "D18",
- "LA20_P": "R9",
- "LA20_N": "R8",
- "LA22_P": "V7",
- "LA22_N": "W8",
- "LA25_P": "W14",
- "LA25_N": "Y14",
- "LA29_P": "T15",
- "LA29_N": "U15",
- "LA31_P": "U16",
- "LA31_N": "V15",
- "LA33_P": "Y17",
- "LA33_N": "AB17",
- "LA32_N": "Y18",
- "LA15_N": "D19",
- "LA19_P": "R11",
- "LA19_N": "T11",
- "LA21_P": "V11",
- "LA21_N": "W11",
- "LA24_P": "AA14",
- "LA24_N": "AB14",
- "LA28_P": "AA16",
- "LA28_N": "AB16",
- "LA30_P": "Y15",
- "LA30_N": "AB15",
- "LA32_P": "W17"
- }),
- ("SMA_GPIO", {
- "P": "B3",
- "N": "A3"
- }),
- ("SMA_USER_CLK", {
- "P": "M20",
- "N": "M19"
- }),
- ("SMA_MGT_CLK", {
- "P": "C11",
- "N": "D11"
- }),
-]
-
-class Platform(XilinxPlatform):
- default_clk_name = "clk200"
- default_clk_period = 5.0
-
- def __init__(self):
- XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")
-
- def create_programmer(self):
- return iMPACT()
+++ /dev/null
-#!/usr/bin/env python3
-
-# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
-# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# License: BSD
-
-import argparse
-
-from migen import *
-
-from litex.boards.platforms import ac701
-
-from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
-from litex.soc.integration.soc_sdram import *
-from litex.soc.integration.builder import *
-
-from litedram.modules import MT8JTF12864
-from litedram.phy import s7ddrphy
-
-from liteeth.phy.a7_gtp import QPLLSettings, QPLL
-from liteeth.phy.a7_1000basex import A7_1000BASEX
-from liteeth.phy.s7rgmii import LiteEthPHYRGMII
-from liteeth.mac import LiteEthMAC
-
-# CRG ----------------------------------------------------------------------------------------------
-
-class _CRG(Module):
- def __init__(self, platform, sys_clk_freq):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
- self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
- self.clock_domains.cd_clk200 = ClockDomain()
-
- # # #
-
- self.cd_sys.clk.attr.add("keep")
- self.cd_sys4x.clk.attr.add("keep")
- self.cd_sys4x_dqs.clk.attr.add("keep")
-
- self.submodules.pll = pll = S7PLL(speedgrade=-1)
- self.comb += pll.reset.eq(~platform.request("cpu_reset"))
- pll.register_clkin(platform.request("clk200"), 200e6)
- pll.create_clkout(self.cd_sys, sys_clk_freq)
- pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
- pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
- pll.create_clkout(self.cd_clk200, 200e6)
-
- self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
-
-# BaseSoC ------------------------------------------------------------------------------------------
-
-class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(100e6), **kwargs):
- platform = ac701.Platform()
- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
- integrated_rom_size=0x8000,
- integrated_sram_size=0x8000,
- **kwargs)
-
- self.submodules.crg = _CRG(platform, sys_clk_freq)
-
- # sdram
- self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
- self.add_csr("ddrphy")
- sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
- self.register_sdram(self.ddrphy,
- sdram_module.geom_settings,
- sdram_module.timing_settings)
-
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
- mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
- }
- mem_map.update(BaseSoC.mem_map)
-
- def __init__(self, phy="rgmii", **kwargs):
- assert phy in ["rgmii", "1000basex"]
- BaseSoC.__init__(self, **kwargs)
-
- if phy == "rgmii":
- self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
- self.platform.request("eth"))
- self.add_csr("ethphy")
- self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
- self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
- self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
- self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
- self.platform.add_false_path_constraints(
- self.crg.cd_sys.clk,
- self.ethphy.crg.cd_eth_rx.clk,
- self.ethphy.crg.cd_eth_tx.clk)
-
- if phy == "1000basex":
- self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
- self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
- self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
- qpll_settings = QPLLSettings(
- refclksel=0b001,
- fbdiv=4,
- fbdiv_45=5,
- refclk_div=1)
- refclk125 = self.platform.request("gtp_refclk")
- refclk125_se = Signal()
- self.specials += \
- Instance("IBUFDS_GTE2",
- i_CEB=0,
- i_I=refclk125.p,
- i_IB=refclk125.n,
- o_O=refclk125_se)
- qpll = QPLL(refclk125_se, qpll_settings)
- self.submodules += qpll
- self.submodules.ethphy = A7_1000BASEX(qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq)
- self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9/62.5e6)
- self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9/62.5e6)
- self.platform.add_false_path_constraints(
- self.crg.cd_sys.clk,
- self.ethphy.txoutclk,
- self.ethphy.rxoutclk)
-
- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
- interface="wishbone", endianness=self.cpu.endianness)
- self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
- self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
- self.add_csr("ethmac")
- self.add_interrupt("ethmac")
-
-# Build --------------------------------------------------------------------------------------------
-def main():
- parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
- builder_args(parser)
- soc_sdram_args(parser)
- parser.add_argument("--with-ethernet", action="store_true",
- help="enable Ethernet support")
- parser.add_argument("--ethernet-phy", default="rgmii",
- help="select Ethernet PHY (rgmii or 1000basex)")
- args = parser.parse_args()
-
- if args.with_ethernet:
- soc = EthernetSoC(args.ethernet_phy, **soc_sdram_argdict(args))
- else:
- soc = BaseSoC(**soc_sdram_argdict(args))
- builder = Builder(soc, **builder_argdict(args))
- builder.build()
-
-
-if __name__ == "__main__":
- main()
+++ /dev/null
-#!/usr/bin/env python3
-
-# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
-# License: BSD
-
-import argparse
-
-from migen import *
-
-from litex.boards.platforms import de10lite
-
-from litex.soc.integration.soc_sdram import *
-from litex.soc.integration.builder import *
-
-from litedram.modules import IS42S16320
-from litedram.phy import GENSDRPHY
-
-# CRG ----------------------------------------------------------------------------------------------
-class _CRG(Module):
- def __init__(self, platform):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain()
- self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
- # # #
-
- self.cd_sys.clk.attr.add("keep")
- self.cd_sys_ps.clk.attr.add("keep")
- self.cd_por.clk.attr.add("keep")
-
- # power on rst
- rst_n = Signal()
- self.sync.por += rst_n.eq(1)
- self.comb += [
- self.cd_por.clk.eq(self.cd_sys.clk),
- self.cd_sys.rst.eq(~rst_n),
- self.cd_sys_ps.rst.eq(~rst_n)
- ]
-
- # sys clk / sdram clk
- clk50 = platform.request("clk50")
- self.comb += self.cd_sys.clk.eq(clk50)
- self.specials += \
- Instance("ALTPLL",
- p_BANDWIDTH_TYPE="AUTO",
- p_CLK0_DIVIDE_BY=1,
- p_CLK0_DUTY_CYCLE=50,
- p_CLK0_MULTIPLY_BY=1,
- p_CLK0_PHASE_SHIFT="-10000",
- p_COMPENSATE_CLOCK="CLK0",
- p_INCLK0_INPUT_FREQUENCY=20000,
- p_INTENDED_DEVICE_FAMILY="MAX 10",
- p_LPM_TYPE = "altpll",
- p_OPERATION_MODE = "NORMAL",
- i_INCLK=clk50,
- o_CLK=self.cd_sys_ps.clk,
- i_ARESET=~rst_n,
- i_CLKENA=0x3f,
- i_EXTCLKENA=0xf,
- i_FBIN=1,
- i_PFDENA=1,
- i_PLLENA=1,
- )
- self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
-
-# BaseSoC ------------------------------------------------------------------------------------------
-
-class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(50e6), **kwargs):
- assert sys_clk_freq == int(50e6)
- platform = de10lite.Platform()
- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
- integrated_rom_size=0x8000,
- **kwargs)
-
- self.submodules.crg = _CRG(platform)
-
- if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
- sdram_module = IS42S16320(self.clk_freq, "1:1")
- self.register_sdram(self.sdrphy,
- sdram_module.geom_settings,
- sdram_module.timing_settings)
-
-# Build --------------------------------------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite")
- builder_args(parser)
- soc_sdram_args(parser)
- args = parser.parse_args()
-
- soc = BaseSoC(**soc_sdram_argdict(args))
- builder = Builder(soc, **builder_argdict(args))
- builder.build()
-
-
-if __name__ == "__main__":
- main()
+++ /dev/null
-#!/usr/bin/env python3
-
-# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
-# License: BSD
-
-import argparse
-
-from migen import *
-
-from litex.boards.platforms import de1soc
-
-from litex.soc.integration.soc_sdram import *
-from litex.soc.integration.builder import *
-
-from litedram.modules import IS42S16320
-from litedram.phy import GENSDRPHY
-
-# CRG ------------------------------------------------------------------
-
-class _CRG(Module):
- def __init__(self, platform):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain()
- self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
- # # #
-
- self.cd_sys.clk.attr.add("keep")
- self.cd_sys_ps.clk.attr.add("keep")
- self.cd_por.clk.attr.add("keep")
-
- # power on rst
- rst_n = Signal()
- self.sync.por += rst_n.eq(1)
- self.comb += [
- self.cd_por.clk.eq(self.cd_sys.clk),
- self.cd_sys.rst.eq(~rst_n),
- self.cd_sys_ps.rst.eq(~rst_n)
- ]
-
- # sys clk / sdram clk
- clk50 = platform.request("clk50")
- self.comb += self.cd_sys.clk.eq(clk50)
- self.specials += \
- Instance("ALTPLL",
- p_BANDWIDTH_TYPE="AUTO",
- p_CLK0_DIVIDE_BY=1,
- p_CLK0_DUTY_CYCLE=50,
- p_CLK0_MULTIPLY_BY=1,
- p_CLK0_PHASE_SHIFT="-3000",
- p_COMPENSATE_CLOCK="CLK0",
- p_INCLK0_INPUT_FREQUENCY=20000,
- p_OPERATION_MODE="ZERO_DELAY_BUFFER",
- i_INCLK=clk50,
- o_CLK=self.cd_sys_ps.clk,
- i_ARESET=~rst_n,
- i_CLKENA=0x3f,
- i_EXTCLKENA=0xf,
- i_FBIN=1,
- i_PFDENA=1,
- i_PLLENA=1,
- )
- self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
-
-# BaseSoC --------------------------------------------------------------
-
-class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(50e6), **kwargs):
- assert sys_clk_freq == int(50e6)
- platform = de1soc.Platform()
- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
- integrated_rom_size=0x8000,
- **kwargs)
-
- self.submodules.crg = _CRG(platform)
-
- if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
- # ISSI IS42S16320D-7TL
- sdram_module = IS42S16320(self.clk_freq, "1:1")
- self.register_sdram(self.sdrphy,
- sdram_module.geom_settings,
- sdram_module.timing_settings)
-
-# Build ----------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC")
- builder_args(parser)
- soc_sdram_args(parser)
- args = parser.parse_args()
-
- soc = BaseSoC(**soc_sdram_argdict(args))
- builder = Builder(soc, **builder_argdict(args))
- builder.build()
-
-
-if __name__ == "__main__":
- main()
+++ /dev/null
-#!/usr/bin/env python3
-
-# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# License: BSD
-
-import argparse
-
-from migen import *
-
-from litex.boards.platforms import de2_115
-
-from litex.soc.integration.soc_sdram import *
-from litex.soc.integration.builder import *
-
-from litedram.modules import IS42S16320
-from litedram.phy import GENSDRPHY
-
-# CRG ------------------------------------------------------------------
-
-class _CRG(Module):
- def __init__(self, platform):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain()
- self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
- # # #
-
- self.cd_sys.clk.attr.add("keep")
- self.cd_sys_ps.clk.attr.add("keep")
- self.cd_por.clk.attr.add("keep")
-
- # power on rst
- rst_n = Signal()
- self.sync.por += rst_n.eq(1)
- self.comb += [
- self.cd_por.clk.eq(self.cd_sys.clk),
- self.cd_sys.rst.eq(~rst_n),
- self.cd_sys_ps.rst.eq(~rst_n)
- ]
-
- # sys clk / sdram clk
- clk50 = platform.request("clk50")
- self.comb += self.cd_sys.clk.eq(clk50)
- self.specials += \
- Instance("ALTPLL",
- p_BANDWIDTH_TYPE="AUTO",
- p_CLK0_DIVIDE_BY=1,
- p_CLK0_DUTY_CYCLE=50,
- p_CLK0_MULTIPLY_BY=1,
- p_CLK0_PHASE_SHIFT="-3000",
- p_COMPENSATE_CLOCK="CLK0",
- p_INCLK0_INPUT_FREQUENCY=20000,
- p_OPERATION_MODE="ZERO_DELAY_BUFFER",
- i_INCLK=clk50,
- o_CLK=self.cd_sys_ps.clk,
- i_ARESET=~rst_n,
- i_CLKENA=0x3f,
- i_EXTCLKENA=0xf,
- i_FBIN=1,
- i_PFDENA=1,
- i_PLLENA=1,
- )
- self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
-
-# BaseSoC --------------------------------------------------------------
-
-class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(50e6), **kwargs):
- assert sys_clk_freq == int(50e6)
- platform = de2_115.Platform()
- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
- integrated_rom_size=0x8000,
- **kwargs)
-
- self.submodules.crg = _CRG(platform)
-
- if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
- # ISSI IS42S16320D-7TL
- sdram_module = IS42S16320(self.clk_freq, "1:1")
- self.register_sdram(self.sdrphy,
- sdram_module.geom_settings,
- sdram_module.timing_settings)
-
-# Build ----------------------------------------------------------------
-
-def main():
- parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115")
- builder_args(parser)
- soc_sdram_args(parser)
- args = parser.parse_args()
-
- soc = BaseSoC(**soc_sdram_argdict(args))
- builder = Builder(soc, **builder_argdict(args))
- builder.build()
-
-
-if __name__ == "__main__":
- main()
def test_simple(self):
platforms = []
# Xilinx
- platforms += ["minispartan6", "sp605"] # Spartan6
- platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", # Artix7
- "ac701"]
+ platforms += ["minispartan6"] # Spartan6
+ platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7
platforms += ["kc705", "genesys2"] # Kintex7
platforms += ["kcu105"] # Kintex Ultrascale
# Altera/Intel
- platforms += ["de10lite"] # Max10
- platforms += ["de0nano", "de2_115"] # Cyclone4
- platforms += ["de1soc"] # Cyclone5
+ platforms += ["de0nano"] # Cyclone4
# Lattice
platforms += ["tinyfpga_bx"] # iCE40
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