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diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 20ad7d32500bae9df40a176d0160e643108303e5..c2018946d89406a0ebcf7b56bb77154699a7600a 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -149,7 +149,7 @@ When Rc=1 is encountered in an SVP64 Context the destination is different (TODO)
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
-At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP svslar may also be adjusted.
+At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 
 ## Single Predication