Cleanup

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f62f627bb01e719ca9626de61943ab226030f2fe..7858b897249293c471f11f61812561322b40e617 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -28,7 +28,6 @@ PRIVATE_NAMESPACE_BEGIN
 void create_ice40_dsp(ice40_dsp_pm &pm)
 {
        auto &st = pm.st_ice40_dsp;
-       Cell* ffO = st.ffO ? st.ffO : st.ffO_lo;
 
 #if 1
        log("\n");
@@ -38,7 +37,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
        log("addAB:  %s\n", log_id(st.addAB, "--"));
        log("muxAB:  %s\n", log_id(st.muxAB, "--"));
-       log("ffO:    %s\n", log_id(ffO, "--"));
+       log("ffO:    %s\n", log_id(st.ffO, "--"));
 #endif
 
        log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -120,8 +119,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
                if (st.ffFJKG)
                        log(" ffFJKG:%s", log_id(st.ffFJKG));
 
-               if (ffO)
-                       log(" ffO:%s", log_id(ffO));
+               if (st.ffO)
+                       log(" ffO:%s", log_id(st.ffO));
 
                log("\n");
        }
@@ -167,9 +166,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        bool accum = false;
        if (st.addAB) {
                if (st.addA)
-                       accum = (ffO && st.addAB->getPort("\\B") == st.sigO);
+                       accum = (st.ffO && st.addAB->getPort("\\B") == st.sigO);
                else if (st.addB)
-                       accum = (ffO && st.addAB->getPort("\\A") == st.sigO);
+                       accum = (st.ffO && st.addAB->getPort("\\A") == st.sigO);
                else log_abort();
                if (accum)
                        log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@@ -219,13 +218,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
        cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
-       if (ffO) {
-               if (st.ffO)
+       if (st.ffO) {
+               if (st.ffO_hilo)
                        cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
                else
                        cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
 
-               ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+               st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
                cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
        }
        else {

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 1219e0d244452923d9abf22aca5361c5d3355e12..95e8da379a0bed7d8d01bd5bfcfd948759570e1e 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -3,7 +3,7 @@ pattern ice40_dsp
 state <SigBit> clock
 state <bool> clock_pol cd_signed
 state <SigSpec> sigA sigB sigCD sigH sigO
-state <Cell*> addAB muxAB
+state <Cell*> addAB muxAB ffO
 
 match mul
        select mul->type.in($mul, \SB_MAC16)
@@ -202,21 +202,21 @@ code muxAB sigO
                sigO = port(muxAB, \Y);
 endcode
 
-match ffO
+match ffO_hilo
        // Ensure that register is not already used
        if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
        // Ensure that OLOADTOP/OLOADBOT is unused or zero
        if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
        if nusers(sigO) == 2
-       select ffO->type.in($dff)
-       filter GetSize(port(ffO, \D)) >= GetSize(sigO)
-       slice offset GetSize(port(ffO, \D))
-       filter offset+GetSize(sigO) <= GetSize(port(ffO, \D)) && port(ffO, \D).extract(offset, GetSize(sigO)) == sigO
+       select ffO_hilo->type.in($dff)
+       filter GetSize(port(ffO_hilo, \D)) >= GetSize(sigO)
+       slice offset GetSize(port(ffO_hilo, \D))
+       filter offset+GetSize(sigO) <= GetSize(port(ffO_hilo, \D)) && port(ffO_hilo, \D).extract(offset, GetSize(sigO)) == sigO
        optional
 endmatch
 
 match ffO_lo
-       if !ffO && GetSize(sigO) > 16
+       if !ffO_hilo && GetSize(sigO) > 16
        // Ensure that register is not already used
        if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
        // Ensure that OLOADTOP/OLOADBOT is unused or zero
@@ -229,19 +229,19 @@ match ffO_lo
        optional
 endmatch
 
-code clock clock_pol sigO sigCD cd_signed
-       Cell* ff = nullptr;
-       if (ffO)
-               ff = ffO;
+code ffO clock clock_pol sigO sigCD cd_signed
+       ffO = nullptr;
+       if (ffO_hilo)
+               ffO = ffO_hilo;
        else if (ffO_lo)
-               ff = ffO_lo;
-       if (ff) {
-               for (auto b : port(ff, \Q))
+               ffO = ffO_lo;
+       if (ffO) {
+               for (auto b : port(ffO, \Q))
                        if (b.wire->get_bool_attribute(\keep))
                                reject;
 
-               SigBit c = port(ff, \CLK).as_bit();
-               bool cp = param(ff, \CLK_POLARITY).as_bool();
+               SigBit c = port(ffO, \CLK).as_bit();
+               bool cp = param(ffO, \CLK_POLARITY).as_bool();
 
                if (clock != SigBit() && (c != clock || cp != clock_pol))
                        reject;
@@ -249,7 +249,7 @@ code clock clock_pol sigO sigCD cd_signed
                clock = c;
                clock_pol = cp;
 
-               sigO.replace(port(ff, \D), port(ff, \Q));
+               sigO.replace(port(ffO, \D), port(ffO, \Q));
 
                // Loading value into output register is not
                //   supported unless using accumulator