<https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
# Other
- https://riscv.org/risc-v-trademark-usage/
-Example 1: https://emb-riscv.github.io/
+Example: https://emb-riscv.github.io/
Implementation proposal that does not comply with the minimal M mode
requirements and may not be RISC-V compliant. The “Embedded RISC-V”
less risky assuming this may or may not be the Foundation’s official
Embedded Working Group? It is hard to tell. It is suggestive.
-Example 2:
-https://github.com/cliffordwolf/xbitmanip/blob/master/xbitmanip-draft.pdf
-
Uses X- prefix, extends the specifications, doesn’t modify the RISC-V
logo. Clearly fair use.